PROGRAMMABLE STRUCTURED ARRAYS

• US 20150077159A1
• Filed: 08/18/2014
• Published: 03/19/2015
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Yakimishu Co Ltd LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 9,397,665 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Claims

1. A method of operating a semiconductor device, said method comprising:

controlling a pass-gate that is in a layer of said device, according to an output of a configuration circuit that is also in said layer of said device;

said pass-gate connecting electrically a first metal line and a second metal line in response to said output having a first state; and

said pass-gate disconnecting electrically said first metal line from said second metal line in response to said output having a second state.

2. The method of claim 1, wherein said controlling comprises receiving, at said pass-gate, a control signal that has a first voltage level if a memory element of said configuration circuit has a first polarity and that has a second voltage level if said memory element has a second polarity.

3. The method of claim 2, further comprising:

configuring polarities of memory elements of said configuration circuit, wherein said polarities are said first polarity or said second polarity;

selectively turning on a first subset of a plurality of pass-gates of said device, and selectively turning off a second subset of said plurality of pass-gates, according to said polarities; and

interconnecting electrically a first plurality of wires of said device and a second plurality of wires of said device in a pattern responsive to said turning on and said turning off.

4. The method of claim 1, wherein said pass-gate and said configuration circuit comprise thin film transistors (TFTs).

5. The method of claim 1, wherein said first metal line and said second metal line are both located on the same side of said layer.

6. The method of claim 1, wherein said first metal line and said second metal line are located on opposite sides of said layer.

7. The method of claim 1, wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of:

fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating.

8. The method of claim 1, wherein said pass-gate is physically connected at one end to said first metal line through a first through-hole via and is physically connected at the other end to said second metal line through a second through-hole via.

9. A method of operating a semiconductor device comprising a plurality of pass-gates, a first plurality of wires, and a second plurality of wires, said method comprising:

turning on a pass-gate of said plurality of pass-gates in response to receiving at said pass-gate an output having a first state from a configuration circuit, wherein said pass-gate and said configuration circuit are in a same layer of said device;

said pass-gate, when turned on, connecting electrically a first metal wire of said first plurality of wires and a second metal wire of said second plurality of wires;

turning off said pass-gate in response to receiving at said pass-gate an output having a second state from said configuration circuit; and

said pass-gate, when turned off disconnecting electrically said first metal wire from said second metal wire.

10. The method of claim 9, further comprising:

setting an output of said configuration circuit to a first voltage level corresponding to said first state if a memory element of said configuration circuit has a first polarity; and

setting an output of said configuration circuit to a second voltage level corresponding to said second state if said memory element has a second polarity.

11. The method of claim 9, further comprising:

selectively turning on a first subset of said plurality of pass-gates and selectively turning off a second subset of said plurality of pass-gates; and

interconnecting electrically said first plurality of wires and said second plurality of wires in a pattern responsive to said turning on and said turning off.

12. The method of claim 11, further comprising tuning on said first subset of said plurality of pass-gates and turning off said second subset of said plurality of pass-gates according to bit values stored in memory elements of said configuration circuit.

13. The method of claim 12, further comprising:

programming said bit values; and

changing said pattern in response to a change in said bit values.

14. The method of claim 9, wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of:

fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating.

15. A method of fabricating a semiconductor device, said method comprising:

forming a first plurality of wires in a first layer of said device;

forming a second plurality of wires in a second layer of said device; and

forming a plurality of pass-gates and a configuration circuit in a third layer of said device between said first layer and said second layer;

wherein said pass-gates are configured to be selectively turned on to enable one or more types of electrical connections, said types of electrical connections comprising;

an electrical connection between two wires in said first layer;

an electrical connection between two wires in said second layer; and

an electrical connection between a wire in said first layer and a wire in said second layer.

16. The method of claim 15, further comprising:

forming a first plurality of through-hole vias coupled to pass-gates in said third layer and also coupled to wires in said first layer, and

forming a second plurality of through-hole vias coupled to pass-gates in said third layer and also coupled to wires in said second layer.

17. The method of claim 15, wherein said pass-gates and said configuration circuit comprise thin film transistors (TFTs).

18. The method of claim 15, wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of:

fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating.

19. The method of claim 15, wherein said first plurality of wires and said second plurality of wires are configured to be electrically interconnected in a pattern responsive to said configuration circuit selectively turning on a first subset of said plurality of pass-gates and selectively turning off a second subset of said plurality of pass-gates.

20. The method of claim 19, wherein said configuration circuit comprises a plurality of memory elements coupled to said plurality of pass-gates, wherein said configuration circuit is configured to turn on said first subset of pass-gates and turn off said second subset of pass-gates according to bit values stored in said memory elements.