MANAGING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS

• US 20150089152A1
• Filed: 09/26/2013
• Published: 03/26/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Cain, Harold W. III, Gschwind, Michael K., Michael, Maged M., Salapura, Valentina, Schwarz, Eric M., Shum, Chung-Lung K.
• Granted Patent: US 9,298,626 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions

Abstract

Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Claims

1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:

executing a first transaction in the computing environment, the first transaction accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;

based on the detecting, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

executing a subsequent transaction in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.

2. The method of claim 1, further comprising:

receiving, from another requestor in the computing environment, a request for the first cache line in the sub-line coherency mode, the request targeting a memory address within the first cache line;

selecting a first sub-cache line portion of the first cache line, the first sub-cache line portion associated with the memory address;

notifying the requestor that only a sub-cache line portion of the first cache line will be returned; and

returning to the requestor the first sub-cache line portion in response to the request.

3. The method of claim 1, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein a second-cache copy of the first cache line in a second cache remains in the full-line coherency mode after the placing the first-cache copy in the sub-line coherency mode.

4. The method of claim 1, further comprising:

marking, while executing the first transaction, a full cache line of the first cache line as transactionally accessed; and

marking, while executing the subsequent transaction, only the relevant sub-cache line portion of the first cache line as transactionally accessed.

5. The method of claim 1, further comprising:

based on the detecting, determining that the first cache line is a high-conflict cache line.

6. The method of claim 5, further comprising:

based on the detecting, incrementing a counter in an entry in a conflict address detection table, the entry associating the counter with the first cache line, wherein the determining that the first cache line is the high-conflict cache line comprises determining that the incremented counter satisfies a high-conflict criterion.

7. A computer system for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

executing a first transaction in the computing environment, the first transaction accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;

based on the detecting, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

executing a subsequent transaction in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.

8. The system of claim 7, wherein the method further comprises:

based on the detecting, determining that the first cache line is a high-conflict cache line.

9. The system of claim 8, wherein the method further comprises:

based on the detecting, incrementing a counter in an entry in a conflict address detection table, the entry associating the counter with the first cache line, wherein the determining that the first cache line is the high-conflict cache line comprises determining that the incremented counter satisfies a high-conflict criterion.

10. The system of claim 9, wherein the determining that the incremented counter satisfies the high-conflict criterion comprises:

determining that the incremented counter has reached a threshold value.

11. The system of claim 9, wherein the determining that the incremented counter satisfies the high-conflict criterion comprises:

calculating a percentage, the percentage based on the incremented counter and a total number of conflicting accesses in the computing environment; and

determining that the percentage has reached a threshold value.

12. The system of claim 9, wherein the method further comprises:

determining that a reset criterion associated with the counter is satisfied;

resetting the counter based on the determining that the reset criterion is satisfied; and

placing the first cache line in the full-line coherency mode based on the determining that the reset criterion is satisfied.

13. The system of claim 12, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of transactions complete;

a number of instructions complete; and

a cache line associated with the counter is cast out of the cache.

14. The system of claim 9, wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

15. The system of claim 9, wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.

16. A computer program product for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

executing a first transaction in the computing environment, the first transaction accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;

based on the detecting, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

executing a subsequent transaction in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.

17. The computer program product of claim 16, wherein the method further comprises:

marking, while executing the first transaction, a full cache line of the first cache line as transactionally accessed; and

marking, while executing the subsequent transaction, only the relevant sub-cache line portion of the first cache line as transactionally accessed.

18. The computer program product of claim 16, wherein the method further comprises:

based on the detecting, determining that the first cache line is a high-conflict cache line.

19. The computer program product of claim 18, wherein the method further comprises:

based on the detecting, incrementing a counter in an entry in a conflict address detection table, the entry associating the counter with the first cache line, wherein the determining that the first cache line is the high-conflict cache line comprises determining that the incremented counter satisfies a high-conflict criterion.

20. The computer program product of claim 19, wherein the method further comprises:

determining that a reset criterion associated with the counter is satisfied;

resetting the counter based on the determining that the reset criterion is satisfied; and

placing the first cache line in the full-line coherency mode based on the determining that the reset criterion is satisfied.