THROTTLING DEVICE POWER

• US 20150089255A1
• Filed: 09/26/2013
• Published: 03/26/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jurski, Janusz, Swanson, Robert, Kumar, Anil, Oriol, Mariusz, Piotrewicz, Waldemar
• Granted Patent: US 9,891,686 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and system for throttling I/O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.

Claims

1. A method for throttling device power demand during critical power events, comprising:

detecting a critical power event; and

issuing a signal to system devices to defer optional transactions during the critical power event.

2. The method of claim 1, comprising:

determining if the critical power event has ended, and, if so,

resuming normal operations.

3. The method of claim 1, comprising detecting an underpower event.

4. The method of claim 1, comprising detecting a thermal excursion of a power supply.

5. The method of claim 1, comprising changing a state of a signal line to indicate an opportunistic buffer flush and fill (OBFF) condition to the system devices.

6. The method of claim 1, comprising issuing a command over a bus to indicate an opportunistic buffer flush and fill (OBFF) condition.

7. The method of claim 1, comprising deferring non-critical interrupts from system devices.

8. The method of claim 1, comprising deferring non-critical dynamic memory accesses (DMA) from system devices.

9. The method of claim 1, comprising allowing critical interrupts from devices.

10. A system for controlling power usage, comprising:

a power-fault detection system;

a plurality of peripheral devices; and

a control system, wherein the control system is configured to receive a signal from the power-fault detection system indicating a power fault and send a signal to the plurality of peripheral devices to defer optional transactions.

11. The system of claim 10, wherein the power-fault detection system comprises a power supply configured to detect a thermal excursion.

12. The system of claim 10, wherein the power-fault detection system is configured to detect a low voltage condition.

13. The system of claim 10, comprising a PCIe bus.

14. The system of claim 10, comprising a signal line coupled to the control system and a peripheral device, wherein the signal line indicates the status of an opportunistic flush and fill (OBFF) condition.

15. The system of claim 10, wherein the control system is configured to issue an opportunistic flush and fill (OBFF) command to a peripheral device over a communications bus.

16. The system of claim 15, comprising a peripheral device coupled to a signal line, wherein the peripheral device is configured to defer optional transactions based, at least in part, on the voltage level applied to the signal line.

17. The system of claim 15, wherein the peripheral device comprises a graphics processing unit (GPU), a gigabit Ethernet card (GbE), a small computer system interface (SCSI), a central processing unit (CPU), a memory device, a switch, or any combinations thereof.

18. The system of claim 10 comprising a switch configured to receive a throttling message over a communications bus and change a voltage on a signal line in response to the throttling message.

19. A system that throttles back power usage in peripheral devices in a computer system, comprising:

a system management engine comprising;

a power detection system; and

an opportunistic buffer flush and fill (OBFF) controller;

a signal line coupling the OBFF controller to a peripheral device;

a communications bus coupling the OBFF controller to a second peripheral device; and

a module comprising code configured to direct the system management engine to detect a power fault and issue an OBFF command to a coupled peripheral device.

20. The system of claim 19, wherein the OBFF command comprises a change in a voltage level on the signal line.

21. The system of claim 19, wherein the OBFF command comprises a command sent over the communications bus.

22. The system of claim 19, wherein the communications bus is a PCIe bus.

23. A non-transitory, computer readable medium comprising code configured to control a node manager to throttle device power demand during critical power events, comprising:

code configured to detecting a critical power event; and

code to direct the node manager to issue a signal to system devices to defer optional transactions during the critical power event.

24. The non-transitory, computer readable medium of claim 23, comprising:

code to direct the node manager to determine if the critical power event has ended, and, if so,

code to direct the node manager to resume normal operations.

25. The non-transitory, computer readable medium of claim 23, comprising code to direct the node manager to detect an under-power event.

26. The non-transitory, computer readable medium of claim 23, comprising code to direct the node manager to detect a thermal excursion of a power supply.

27. The non-transitory, computer readable medium of claim 23, comprising code to direct the node manager to change a state of a signal line to indicate an opportunistic buffer flush and fill (OBFF) condition to the system devices.

28. The non-transitory, computer readable medium of claim 23, comprising code to direct the node manager to issue a command over a bus to indicate an opportunistic buffer flush and fill (OBFF) condition.