SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20150091008A1
• Filed: 12/11/2014
• Published: 04/02/2015
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YOKOI, Tomokazu, YAMANE, Yasumasa
• Granted Patent: US 10,192,990 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a crystalline oxide semiconductor layer;

forming a first insulating layer over the crystalline oxide semiconductor layer;

forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween;

forming a gate insulating layer by etching the first insulating layer with the gate electrode used as a mask; and

forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on part of the crystalline oxide semiconductor layer, the part is not covered with the gate insulating layer.

2. A method of manufacturing a semiconductor device, comprising:

forming an oxide semiconductor layer;

forming a first insulating layer over the oxide semiconductor layer;

forming a crystalline oxide semiconductor layer by performing heat treatment on the oxide semiconductor layer;

forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween;

forming a gate insulating layer by etching the first insulating layer with the use of the gate electrode as a mask;

forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on part of the crystalline oxide semiconductor layer, the part is not covered with the gate insulating layer;

forming a second insulating layer covering the crystalline oxide semiconductor layer and the gate electrode;

forming, in the second insulating layer, openings in regions overlapping with a source region and a drain region; and

forming, over the second insulating layer, a source electrode and a drain electrode respectively in contact with the source region and the drain region through the openings.

3. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a crystalline oxide semiconductor layer over the gate electrode with the gate insulating layer positioned therebetween, the crystalline oxide semiconductor layer comprising an n-type source region, an n-type drain region, and a channel formation region; and

a channel protective layer overlapping with the channel formation region.

4. The semiconductor device according to claim 3, further comprising:

a source electrode in contact with the channel protective layer and the n-type source region; and

a drain electrode in contact with the channel protective layer and the n-type drain region.

5. The semiconductor device according to claim 3,

wherein the n-type source region and the n-type drain region are nitrided regions.

6. The semiconductor device according to claim 3, the gate insulating layer includes an oxygen-excess region, and the channel protective layer includes an oxygen-excess region.