FREQUENCY SHIFTING FOR SIMULTANEOUS ACTIVE MATRIX DISPLAY UPDATE AND IN-CELL CAPACITIVE TOUCH

• US 20150091864A1
• Filed: 09/30/2014
• Published: 04/02/2015
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: Omnivision TDDI Ontario Limited Partnership
• Original Assignee: Synaptics Incorporated
• Inventors: REYNOLDS, Joseph Kurth
• Granted Patent: US 9,442,615 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

Embodiments generally provide a method, input device, and processing system for frequency shifting for synchronized display updating and capacitive sensing. The method includes driving a display signal onto at least one display electrode for updating a display. The method further includes driving a first capacitive sensing signal having a first frequency onto at least one sensor electrode, wherein the first frequency is synchronized to the display signal. The method further includes driving a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ and a timing of the display signal is adjusted to maintain synchronization with the second frequency, and wherein each capacitive sensing signal and the display signal are driven in parallel for at least some period of time.

Claims

1. An input device comprising:

a plurality of display electrodes;

a plurality of sensor electrodes; and

a processing system coupled to the plurality of display electrodes and to the plurality of sensor electrodes, wherein the processing system is configured to;

drive a display signal onto at least one of the plurality of display electrodes for updating a display,

drive a first capacitive sensing signal having a first frequency onto at least one of the plurality of sensor electrodes, wherein the first frequency is synchronized to the display signal, and

drive a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ and a timing of the display signal is adjusted to maintain synchronization with the second frequency,

wherein each capacitive sensing signal and the display signal are driven in parallel for at least some period of time.

2. The input device of claim 1, wherein the timing of the display signal is further adjusted to maintain synchronization with a phase of the second capacitive sensing signal, wherein the phase of the second capacitive sensing signal is different from a phase of the first capacitive sensing signal.

3. The input device of claim 1, wherein the frequency of the capacitive sensing signal defines a sensing cycle comprising two half cycles, wherein a duration of the half cycles is synchronized to the display signal.

4. The input device of claim 1, wherein the timing of the display signal includes a line rate for a gate line used to activate a row of display pixels.

5. The input device of claim 4, wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

6. The input device of claim 4, wherein adjusting the timing of the display signal includes delaying a turn-on time for the gate line.

7. The input device of claim 1, wherein the processing system further comprises a display line buffer having a size based on a length of a capacitive sensing period and a difference in a host pixel rate and a display update rate.

8. The input device of claim 1, wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.

9. A processing system, comprising:

a display module configured to drive a display signal onto at least one of a plurality of display electrodes for updating a display; and

a sensing module configured to;

drive a first capacitive sensing signal having a first frequency onto at least one of the plurality of sensor electrodes, wherein the first frequency is synchronized to the display signal,

drive a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ and a timing of the display signal is adjusted to maintain synchronization with the second frequency,

wherein the capacitive sensing signal and the display signal are driven in parallel for at least some period of time.

10. The processing system of claim 9, wherein the frequency of the capacitive sensing signal defines a sensing cycle comprising two half cycles, wherein a duration of the half cycles is synchronized to the display signal.

11. The processing system of claim 9, wherein the timing of the display signal includes a line rate for a gate line used to activate a row of display pixels.

12. The processing system of claim 11, wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

13. The processing system of claim 11, wherein adjusting the timing of the display signal includes delaying a turn-on time for the gate line.

14. The processing system of claim 9, wherein the processing system further comprises a display line buffer having a size based on a length of a capacitive sensing period and a difference in a host pixel rate and a display update rate.

15. The processing system of claim 9, wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.

16. A method, comprising:

driving a display signal onto at least one of a plurality of display electrodes for updating a display,

driving a first capacitive sensing signal having a first frequency onto at least one of a plurality of sensor electrodes, wherein the first frequency is synchronized to the display signal, and

driving a second capacitive sensing signal having a second frequency onto the at least one sensor electrode, wherein the first and second frequencies differ and a timing of the display signal is adjusted to maintain synchronization with the second frequency,

wherein each capacitive sensing signal and the display signal are driven in parallel for at least some period of time.

17. The method of claim 16, wherein the frequency of the capacitive sensing signal defines a sensing cycle comprising two half cycles, wherein a duration of the half cycles is synchronized to the display signal.

18. The method of claim 16, wherein the timing of the display signal includes a line rate for a gate line used to activate a row of display pixels.

19. The method of claim 18, wherein the difference between the first and second frequencies results from varying an amount of time between display updates of sub-pixels in the activated row.

20. The method of claim 18, wherein adjusting the timing of the display signal includes delaying a turn-on time for the gate line.

21. The method of claim 16, wherein adjusting the timing of the display signal is performed using a display line buffer having a size based on a length of a capacitive sensing period and a difference in a host pixel rate and a display update rate.

22. The method of claim 16, wherein at least one of the plurality of sensor electrodes comprises at least one of the plurality of display electrodes.