Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor

• US 20150092486A1
• Filed: 12/08/2014
• Published: 04/02/2015
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 9,589,963 B2
• Time in Patent Office: Days
• US Class Current: 365/177
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Claims

1-19. -19. (canceled)

20. A multi-port semiconductor memory cell comprising:

a plurality of gates;

a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and

a plurality of conductive regions of a second conductivity type,

wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;

wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and

wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.

21. The multi-port semiconductor memory cell of claim 20, wherein the plurality of conductive regions is in electrical communication with the common body region, and further wherein each of the plurality of conductive regions is spaced apart from the other of the plurality of conductive regions.

22. The multi-port semiconductor memory cell of claim 20, wherein at least a portion of the common body region separates each of the plurality of conductive regions from the others of the plurality of conductive regions.

23. The multi-port semiconductor memory cell of claim 20, wherein the multi-port semiconductor memory cell includes a total number of ports, wherein said plurality of conductive regions comprises a total number of conductive regions, and wherein said plurality of gates comprises a total number of gates, wherein the total number of ports is equal to the total number of gates, and further wherein the total number of conductive regions is one more than the total number of gates.

24. The multi-port semiconductor memory cell of claim 23, wherein one of said ports is configured to perform a holding operation.

25. The multi-port semiconductor memory cell of claim 20, wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

26. The multi-port semiconductor memory cell of claim 20, wherein said voltage applied to said back bias terminal is a constant positive voltage bias.

27. The multi-port semiconductor memory cell of claim 20, wherein said voltage applied to said back bias terminal is a periodic pulse of positive voltage.

28. A semiconductor memory cell comprising:

a plurality of bipolar devices; and

a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;

wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;

wherein said common base region is shared among said plurality of bipolar devices; and

wherein one of said plurality of bipolar devices is configured to maintain the charge stored in said common base region.

29. The semiconductor memory cell of claim 28, wherein said common base region stores at least two stable charge levels.

30. The semiconductor memory cell of claim 28, further comprising a plurality of gates.

31. The semiconductor memory cell of claim 28, wherein the semiconductor memory cell includes ports, wherein a total number of said ports is equal to a total number of said bipolar devices.

32. The semiconductor memory cell of claim 28, wherein the semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common base region.

33. A semiconductor memory cell comprising:

a substrate region;

a plurality of gates;

a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;

a plurality of conductive regions of a second conductivity type,

wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions; and

an insulator layer located beneath said common body region insulating said common body region from the substrate;

wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and

wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.

34. The multi-port semiconductor memory cell of claim 33, wherein the plurality of conductive regions is in electrical communication with the common body region, and further wherein each of the plurality of conductive regions is spaced apart from the other of the plurality of conductive regions.

35. The multi-port semiconductor memory cell of claim 33, wherein at least a portion of the common body region separates each of the plurality of conductive regions from the others of the plurality of conductive regions.

36. The multi-port semiconductor memory cell of claim 33, wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

37. The multi-port semiconductor memory cell of claim 33, wherein said voltage applied to said back bias terminal is a constant positive voltage bias.

38. The multi-port semiconductor memory cell of claim 33, wherein said voltage applied to said back bias terminal is a periodic pulse of positive voltage.