SYSTEM AND METHOD FOR BANK LOGICAL DATA REMAPPING

• US 20150095546A1
• Filed: 10/02/2013
• Published: 04/02/2015
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Bennett, Alan, Gorobets, Sergey Anatolievich
• Granted Patent: US 9,336,129 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0649 Lifecycle management

Abstract

A method and system are disclosed for remapping logical addresses between memory banks of discrete or embedded multi-bank storage device. The method may include a controller of a storage device tracking a total erase count for a storage device, determining if an erase count imbalance greater than a threshold exists between banks, and then remapping logical address ranges from the highest erase count bank to the lowest erase count bank to even out wear between the banks. The system may include a controller that may maintain a bank routing table, an erase counting mechanism and execute instructions for triggering a remapping process to remap an amount of logical addresses such that an address range is reduced for a hotter bank and increased for a colder bank.

Claims

1. A method of remapping storage of content between memory banks in a storage device, the method comprising:

in a storage device having a controller in communication with non-volatile memory, wherein the non-volatile memory comprises a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses, the controller;

detecting a bank remapping review event;

in response to detecting the bank remapping review event, determining a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and

when the difference in erase counts exceeds a predetermined threshold, remapping logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank.

2. The method of claim 1, further comprising copying any valid data associated with the remapped logical block addresses from the first memory bank to the second memory bank.

3. The method of claim 1, wherein detecting the bank remapping review event comprises determining if a total erase count for the plurality of memory banks in the storage device exceeds a predetermined storage device erase count.

4. The method of claim 3, wherein the total erase count for the storage device comprises an erase count for only multi-level cell (MLC) flash memory cells in the plurality of memory banks.

5. The method of claim 1, wherein remapping logical block addresses comprises the controller of the storage device selecting a range of logical block addresses associated with the first memory bank and changing an association of the selected range of logical block addresses from the first bank to the second bank such that a total logical block address range associated with the first bank is reduced and a total logical block address range associated with the second bank is increased.

6. The method of claim 5, wherein the controller first selects any logical block addresses from the memory first bank associated with logically erased data when selecting the range of logical block addresses, wherein logically erased data comprises data marked as obsolete prior to physical erase.

7. The method of claim 5, wherein the controller selects logical block addresses for data most recently written to the first bank for the range of logical block addresses.

8. The method of claim 5, wherein the controller selects logical block addresses associated with valid data and associates the selected logical block addresses to the second bank without copying the valid data from the first bank to the second bank, wherein the controller diverts data associated with the selected logical block addresses that is received in a subsequent host write command to the second bank.

9. The method of claim 5, further comprising the controller updating an address table in the first memory bank to remove the range of logical block addresses, and updating an address table of the second memory bank to add the range of logical block addresses, wherein a total amount of used logical addresses associated with the first memory bank is reduced and a total amount of used logical block addresses associated with the second memory bank is increased.

10. The method of claim 1, wherein the predetermined threshold between the highest erase count and the lowest erase count of the plurality of memory banks comprises at least a five percent difference between the highest erase count and the lowest erase count.

11. A storage device comprising:

a non-volatile memory having a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses; and

a controller in communication with the plurality of memory banks, the controller configured to;

detect a bank remapping review event;

in response to detecting the bank remapping review event, determine a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and

when the difference the highest and lowest erase counts exceeds a predetermined threshold;

remap logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank.

12. The storage device of claim 11, wherein the controller is further configured to copy any valid data associated with the remapped logical block addresses from the first memory bank to the second memory bank.

13. The storage device of claim 11, wherein the controller is configured to detect the bank remapping review event by determining if a total erase count for the plurality of memory banks in the storage device exceeds a predetermined storage device erase count.

14. The storage device of claim 13, wherein the total erase count for the storage device comprises an erase count for only multi-level cell (MLC) flash memory cells in the plurality of memory banks.

15. The storage device of claim 11, wherein to remap logical block addresses the controller of the storage device is configured to select a range of logical block addresses associated with the first memory bank and change an association of the selected range of logical block addresses from the first bank to the second bank.

16. The storage device of claim 15, wherein the controller is configured to first select any logical block addresses associated with trimmed data from the first memory bank when selecting the range of logical block addresses, wherein trimmed data comprises data marked as obsolete prior to erase.

17. The storage device of claim 15, wherein the controller is configured to select logical block addresses for data most recently written to the first bank for the range of logical block addresses.

18. The storage device of claim 15, wherein the controller is configured to select logical block addresses associated with valid data and associate the selected logical block addresses to the second bank without copying the valid data from the first bank to the second bank, wherein the controller is configured to divert data associated with the selected logical block addresses received in a subsequent host write command to the second bank.

19. The storage device of claim 15, wherein the controller is further configured to update an address table of the first memory bank to remove the range of logical block addresses, and update an address table of the second memory bank to add the range of logical block addresses, wherein a total amount of used logical addresses associated with the first memory bank is reduced and a total amount of used logical block addresses associated with the second memory bank is increased.

20. The storage device of claim 19, wherein the address table of the first memory bank is in the first memory bank and wherein the address table of the second memory bank is in the second memory bank.

21. The storage device of claim 11, wherein the predetermined threshold between the highest erase count and the lowest erase count of the plurality of memory banks comprises a five percent difference between the highest erase count and the lowest erase count.

22. A storage device comprising:

a non-volatile memory having a plurality of memory banks and wherein each of the plurality of memory banks is associated with a respective unique range of logical block addresses; and

a controller in communication with the plurality of memory banks, the controller configured to;

detect a bank remapping review event;

in response to detecting the bank remapping review event, determine a difference in erase counts between a first memory bank having a highest erase count in the plurality of memory banks and a second memory bank having a lowest erase count in the plurality of memory banks; and

when the difference the highest and lowest erase counts exceeds a predetermined threshold;

remap logical block addresses from a first range of logical block addresses associated with the first memory bank to a second range of logical block addresses associated with the second memory bank;

in response to detecting the bank remapping review event, determine a difference in erase counts between a third memory bank having a second highest erase count in the plurality of memory banks and a fourth memory bank having a second lowest erase count in the plurality of memory banks; and

when the difference the second highest and second lowest erase counts exceeds a predetermined threshold;

remap logical block addresses from a third range of logical block addresses associated with the third memory bank to a fourth range of logical block addresses associated with the fourth memory bank.

23. The storage device of claim 22, wherein the controller is configured to remap an amount of logical block addresses from the first memory bank to the second memory bank by updating a bank routing table maintained in the storage device to reduce a range of logical block addresses associated with the first memory bank and to increase the range of logical block addresses associated with the second memory bank.