UTILIZING DESTRUCTIVE FEATURES AS RAM CODE FOR A STORAGE DEVICE

• US 20150100722A1
• Filed: 11/25/2013
• Published: 04/09/2015
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: WEBSTER, MICHAEL W.
• Granted Patent: US 9,275,697 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: A63C 17/008 with retractable wheel, i.e. movable relative to the chassis out of contact from surface
• CPC Class Codes: B60L 15/2009 for braking
• CPC Class Codes: B60L 15/2036 Electric differentials, e.g. for supporting steering vehicles
• CPC Class Codes: B60L 2200/16 Single-axle vehicles
• CPC Class Codes: B60L 2220/44 Wheel Hub motors, i.e. integrated in the wheel hub
• CPC Class Codes: B60L 2240/12 Speed
• CPC Class Codes: B60L 2240/20 angular
• CPC Class Codes: B60L 2240/22 Yaw angle
• CPC Class Codes: B60L 2240/26 Vehicle weight
• CPC Class Codes: B60L 2240/421 Speed
• CPC Class Codes: B60L 2270/145 Structure borne vibrations
• CPC Class Codes: B60L 3/0076 relating to braking
• CPC Class Codes: B62D 31/006 foldable droppable B60F5/006
• CPC Class Codes: B62D 51/02 the driver standing in the vehicle
• CPC Class Codes: B62K 11/007 Automatic balancing machines with single main ground engaging wheel or coaxial wheels supporting a rider
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/4411 : Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02T 10/64 : Electric machine technologies in electromobility
• CPC Class Codes: Y02T 10/70 : Energy storage systems for electromobility, e.g. batteries
• CPC Class Codes: Y02T 10/72 : Electric energy management in electromobility

Abstract

A host including a controller configured to be connected to a storage device separate from the host. The controller is configured to maintain random access memory (RAM) code on the host, the RAM code configured to provide a destructive function, temporarily load the RAM code onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform a destructive function on the storage device, and remove the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.

Claims

1. A host comprising:

a controller configured to be connected to a storage device separate from the host and to;

maintain random access memory (RAM) code on the host, the RAM code configured to provide a destructive function;

temporarily load the RAM code onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform a destructive function on the storage device; and

remove the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.

2. The host of claim 1 wherein the destructive function is configured to perform a first action to render the storage device inoperable until a second action is performed to render the storage device operable.

3. The host of claim 2 wherein the processor is further configured to perform the destructive function on data stored in a memory in the storage device.

4. The host of claim 3 wherein the controller is further configured perform the second action to render the storage device operable, wherein the second action comprises loading replacement data onto the memory in the storage device.

5. The host of claim 4 wherein the data comprises firmware and the memory in the storage device comprises flash memory.

6. The host of claim 5 wherein the replacement data comprises a new copy of the firmware.

7. The host of claim 6 wherein the remove the loaded RAM code from the volatile memory further comprises reboot the storage device.

8. The host of claim 1 wherein the destructive function is configured to improve performance characteristics of a storage unit in the storage device.

9. The host of claim 1 wherein the destructive function is configured to set heat removal operations for the storage device.

10. The host of claim 1 further comprising a memory configured to store an original RAM code, wherein the loaded RAM code comprises a removable copy of the original RAM code.

11. A method for manufacturing a storage device comprising:

maintaining random access memory (RAM) code on an external host separate from the storage device, the RAM code configured to provide a destructive function;

temporarily loading the RAM code from the external host onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform the destructive function on the storage device; and

removing the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.

12. The method of claim 11 wherein the destructive function is configured to perform a first action to render the storage device inoperable until a second action is performed to render the storage device operable.

13. The method of claim 12 wherein the processor is further configured to perform the destructive function on data stored in a memory in the storage device.

14. The method of claim 13 further comprising performing the second action to render the storage device operable, wherein the second action comprises loading replacement data onto the memory in the storage device.

15. The method of claim 14 wherein the data comprises firmware and the memory in the storage device comprises flash memory.

16. The method of claim 15 wherein the replacement data comprises a new copy of the firmware.

17. The method of claim 16 wherein the removing the loaded RAM code from the volatile memory further comprises loading the new copy of the firmware onto the volatile memory.

18. The method of claim 16 wherein the removing the loaded RAM code from the volatile memory further comprises rebooting the storage device.

19. The method of claim 15 further comprising:

rebooting the storage device; and

executing a read only memory (ROM) program stored in a non-volatile memory in the storage device using the processor when the storage device is rebooted, wherein the ROM program causes the processor to load the replacement data onto the volatile memory.

20. The method of claim 11 wherein the destructive function is configured to improve performance characteristics of a storage unit in the storage device.

21. The method of claim 11 wherein the destructive function is configured to set heat removal operations for the storage device.

22. The method of claim 11 further comprising storing an original RAM code in a memory in the external host, wherein the loaded RAM code comprises a removable copy of the original RAM code.

23. A non-transitory machine readable medium storing a program which when executed by a processor in a host, causes the processor in the host to configure a storage device separate from the host by:

maintaining a random access memory (RAM) code on the host, the RAM code configured to provide a destructive function;

temporarily loading the RAM code from the host onto a volatile memory in the storage device during a manufacturing process, wherein the loaded RAM code, when executed by a processor in the storage device, is configured to cause the processor in the storage device to perform a destructive function on the storage device; and

removing the loaded RAM code from the volatile memory after the manufacturing process, wherein the destructive function is unable to be performed by the processor when the loaded RAM code is removed from the volatile memory.

24. The non-transitory machine readable medium of claim 23 wherein the destructive function is configured to perform a first action to render the storage device inoperable until a second action is performed to render the storage device operable.

25. The non-transitory machine readable medium of claim 24 wherein the processor in the storage device is further configured to perform the destructive function on data stored in a memory in the storage device.

26. The non-transitory machine readable medium of claim 24 wherein the program further causes the processor in the host to further configure the storage device by performing the second action to render the storage device operable, wherein the second action comprises loading replacement data onto the memory in the storage device.