Semiconductor Device

• US 20150108540A1
• Filed: 09/19/2014
• Published: 04/23/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Ogawa, Kazuko, Kawashiri, Satoshi
• Granted Patent: US 9,276,095 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region; a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region, and a second main electrode, which is electrically connected to the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger.

Claims

1. A semiconductor device comprising:

a first semiconductor region, which has a first conductivity type;

a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region;

a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region;

a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region;

an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region;

a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region;

a first main electrode, which is electrically connected to the first semiconductor region, and

a second main electrode, which is electrically connected to the fourth semiconductor region,

wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger.

3. The semiconductor device according to claim 1,

wherein the recess is configured by a plurality of recesses arranged in parallel, and the plurality of adjacent recesses is connected to each other by a connection recess, and

wherein the connection recess is formed to extend from an upper surface of the third semiconductor region and to reach the second semiconductor region with penetrating the third semiconductor region.

4. The semiconductor device according to claim 3,

wherein the recess is configured by a plurality of recesses arranged in parallel, and the plurality of adjacent recesses is connected to each other by a connection recess, and

wherein the connection recess is formed to extend from an upper surface of the third semiconductor region and to reach the second semiconductor region with penetrating the third semiconductor region, extends in an arrangement direction of the plurality of recesses, and is connected to an end portion of a recess arranged at the outermost side of the plurality of recesses.

5. The semiconductor device according to claim 1,

wherein the recess is configured by a plurality of recesses arranged in parallel, and the plurality of adjacent recesses is connected to each other by a connection recess,

wherein the connection recess comprises a first connection recess connected to one end portions of the plurality of recesses and a second connection recess connected to the other end portions of the plurality of recesses,

wherein the first connection recess and the second connection recess are respectively formed to extend from an upper surface of the third semiconductor region and to reach the second semiconductor region with penetrating the third semiconductor region, extend in an arrangement direction of the plurality of recesses and are connected to an end portion of a recess arranged at the outermost side of the plurality of recesses, and

wherein the plurality of recesses is arranged in a region in which the first connection recess and the second connection recess face each other, as viewed from a plan view.

6. The semiconductor device according to claim 1,

wherein the recess is configured by a plurality of recesses arranged in parallel, and the plurality of adjacent recesses is connected to each other by a connection recess,

wherein the connection recess is formed to extend from an upper surface of the third semiconductor region and to reach the second semiconductor region with penetrating the third semiconductor region, and

wherein a width of the connection recess is wider than an interval between the adjacent recesses.

7. The semiconductor device according to claim 1,

wherein the recess is configured by a plurality of recesses arranged in parallel, and the plurality of adjacent recesses is connected to each other by a connection recess,

wherein the connection recess is formed to extend from an upper surface of the third semiconductor region and to reach the second semiconductor region with penetrating the third semiconductor region, and

wherein a width of the connection recess is narrower than the width of the recess.

8. The semiconductor device according to claim 1,

wherein the control electrode comprises a first control electrode and a second control electrode provided on a first side surface of the recess and a second side surface facing the first side surface and arranged to face the third semiconductor region with interposing the insulation film,

wherein the recess extends in a stripe shape, as viewed from a plan view, and

wherein lengths of the first side surface and the second side surface in an extension direction of the recess are larger than a facing interval between the first side surface and the second side surface.

9. The semiconductor device according to claim 1,

wherein the control electrode comprises a first control electrode and a second control electrode provided on a first side surface of the recess and a second side surface facing the first side surface and arranged to face the third semiconductor region with the insulation film being interposed therebetween, and

wherein the first control electrode and the second control electrode extend in an extension direction of the recess and reach a connection recess.

10. The semiconductor device according to claim 1,

wherein the width of the recess is 3 μ

m to 15 μ

m, a depth of the recess is 2 μ

m to 10 μ

m, a thickness of the second semiconductor region is 40 μ

m to 140 μ

m, and a specific resistance of the second semiconductor region is 10 Ω

cm to 150 Ω

cm.

11. The semiconductor device according to claim 1,

wherein the width of the recess is larger than a depth of the recess and the width of the recess is 3 to 15 μ

m.

2. A semiconductor device comprising:

a first semiconductor region, which has a first conductivity type;

a second semiconductor region, which has a second conductivity type and which arranged on the first semiconductor region;

a third semiconductor region, which has the first conductivity type and which is arranged on the second semiconductor region;

a fourth semiconductor region, which has the second conductivity type and which is arranged on the third semiconductor region;

an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region;

a control electrode arranged on the insulation film on a side surface of the recess and facing the third semiconductor region;

a first main electrode electrically connected to the first semiconductor region, and

a second main electrode electrically connected to the fourth semiconductor region,

wherein a ratio of a total area of the recess on an extension of an interface between the second semiconductor region and the third semiconductor region to a total area of a region of the third semiconductor region contacting the second main electrode is 1 or larger.