SEMICONDUCTOR MEMORY APPARATUS AND TEMPERATURE CONTROL METHOD THEREOF

• US 20150109856A1
• Filed: 01/17/2014
• Published: 04/23/2015
• Est. Priority Date: 10/22/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Seung Yun, PARK, Hae Chan, KIM, Myoung Sub, LEE, Se Ho
• Granted Patent: US 9,236,121 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Claims

1. A semiconductor memory apparatus, comprising:

a temperature adjustment unit suitable for adjusting a temperature of a memory cell; and

a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

2. The semiconductor memory apparatus of claim 1, wherein a temperature adjustment unit is included in a cell area of the semiconductor memory apparatus together with the memory cell, and the temperature control unit is included in a peripheral circuit area thereof.

3. The semiconductor memory apparatus of claim 2, further comprising, in the cell region:

a semiconductor substrate;

a word line region formed on the semiconductor substrate;

a switching device formed on the word line region;

a data storage region formed on the switching device; and

a metal line region formed on the data storage region,

wherein the temperature adjustment unit is formed on the metal line region.

4. The semiconductor memory apparatus of claim 3, further comprising:

a buffer layer formed between the metal line region and the temperature adjustment unit and suitable for insulating the metal line region from the temperature adjustment unit.

5. The semiconductor memory apparatus of claim 1, wherein the temperature adjustment unit includes a material of which a resistance value is reduced when a temperature thereof is increased or a material of which a resistance value is increased when the temperature thereof is increased.

6. The semiconductor memory apparatus of claim 3, wherein the data storage region includes:

a bottom electrode formed on the switching device;

a data storage unit formed on the bottom electrode; and

a top electrode formed on the data storage unit.

7. The semiconductor memory apparatus of claim 6, wherein the data storage unit is formed of a phase-change material.

8. The semiconductor memory apparatus of claim 2, further comprising, in the cell region:

a semiconductor substrate including the temperature adjustment unit on a rear surface thereof;

a word line region formed on the semiconductor substrate;

a switching device formed on the word line region;

a data storage region formed on the switching device; and

a metal line region formed on the data storage region.

9. The semiconductor memory apparatus of claim 8, further comprising:

a first buffer layer formed between the rear surface of the semiconductor substrate and the temperature adjustment unit; and

a second buffer layer formed on the temperature adjustment unit.

10. The semiconductor memory apparatus of claim 8, wherein the temperature adjustment unit includes a material of which a resistance value is reduced when a temperature thereof is increased or a material of which a resistance value is increased when the temperature thereof is increased.

11. The semiconductor memory apparatus of claim 8, wherein the data storage region includes:

a bottom electrode formed on the switching device;

a data storage unit formed on the bottom electrode; and

a top electrode formed on the data storage unit.

12. The semiconductor memory apparatus of claim 11, wherein the data storage unit is formed of a phase-change material.

13. The semiconductor memory apparatus of claim 1, wherein the temperature control unit includes:

a temperature sensing unit suitable for sensing the temperature of the temperature adjustment unit;

a control unit suitable for receiving the sensed temperature of the temperature sensing unit and generating a control signal to control the temperature of the temperature adjustment unit; and

a current supply unit suitable for supplying current to the temperature adjustment unit in response to the control signal.

14. The semiconductor memory apparatus of claim 13, wherein the temperature adjustment unit and the temperature sensing unit include a same material of which a resistance value is reduced or increased when a temperature thereof is increased.

15. The semiconductor memory apparatus of claim 14, wherein the temperature adjustment unit and the temperature sensing unit are simultaneously formed during a same manufacturing process of the semiconductor memory apparatus.

16. The semiconductor memory apparatus of claim 13, wherein the temperature sensing unit includes a thermister.

17. A method of controlling a temperature of a semiconductor memory apparatus, the method comprising:

measuring a temperature of a cell area of the semiconductor memory apparatus;

comparing a measured temperature of the cell area with a reference temperature range;

determining whether or not the measured temperature of the cell area is in the reference temperature range based on a result of the comparing; and

heating the cell area for a set time based on a result of the determining of the measured temperature of the cell area.

18. The method of claim 17, wherein the controlling of the temperature of the semiconductor memory apparatus is repeated until the measured temperature of the cell area is in the reference temperature range.

19. The method of claim 17, wherein the heating of the cell area for the set time comprises:

supplying a current to the cell area when the measured temperature of the cell area is lower than the reference temperature range; and

determining whether or not a heating time of cell area reach the set time.

20. The method of claim 17, wherein the determining of the measured temperature of the cell area comprises:

terminating the controlling of the temperature of the semiconductor memory apparatus when the measured temperature of the cell area is in the reference temperature range.