BALANCING VOLTAGES BETWEEN BATTERY BANKS

• US 20150123618A1
• Filed: 01/12/2015
• Published: 05/07/2015
• Est. Priority Date: 08/05/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Athas, William C., Greening, Thomas C.
• Granted Patent: US 9,601,932 B2
• Time in Patent Office: Days
• US Class Current: 320/118
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02J 7/0019 using switched or multiplexed charge circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A system that balances voltages between battery banks. The system includes battery banks, including a first bank and a second bank, and a first capacitor. The system also includes a first set of switching devices which selectively couple first and second terminals of the first capacitor to first and second terminals of the first bank, and to first and second terminals of the second bank. The system includes a clocking circuit which generates clock signals with substantially non-overlapping first and second clock phases. This clocking circuit is configured so that during the first phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the first bank, respectively, and during the second phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the second bank, respectively.

Claims

1. A system that balances voltages between battery banks, comprising:

a plurality of battery banks, including a first bank and a second bank;

a first capacitor with a first terminal and a second terminal;

a second capacitor with a first terminal and a second terminal;

a first set of switching devices which selectively couple the first and second terminals of the first capacitor to first and second terminals of the first bank, and first and second terminals of the second bank;

a second set of switching devices which selectively couple the first and second terminals of the second capacitor to the first and second terminals of the first bank, and the first and second terminals of the second bank; and

a clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase;

wherein the clocking circuit is configured to;

control the first set of switching devices, so that during the first phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the first bank, respectively, and during the second phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the second bank, respectively; and

control the second set of switching devices, so that during the first phase the first and second terminals of the second capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the second capacitor are coupled to the first and second terminals of the first bank, respectively.

2. The system of claim 1, wherein each battery bank includes one or more battery cells, wherein if a battery bank comprises multiple battery cells, the multiple battery cells are electrically coupled in parallel.

3. The system of claim 1, wherein the plurality of battery cells are electrically coupled in series to form a battery pack.

4. The system of claim 1, wherein the first set of switching devices includes:

a first switch which couples the first terminal of the first capacitor to the first terminal of the first bank during the first phase;

a second switch which couples the second terminal of the first capacitor to the second terminal of the first bank during the first phase;

a third switch which couples the first terminal of the first capacitor to the first terminal of the second bank during the second phase; and

a fourth switch which couples the second terminal of the first capacitor to the second terminal of the second bank during the second phase.

5. The system of claim 1,

wherein the plurality of banks also includes a third bank which is electrically coupled in series with the first bank and the second bank;

wherein the system additionally comprises a third capacitor with a first terminal and a second terminal; and

wherein the first set of switching devices and the clocking circuit are configured so that during the first phase the first and second terminals of the third capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the third capacitor are coupled to the first and second terminals of the third bank, respectively.

6. The system of claim 1, wherein the clocking circuit is a resonant LC oscillator circuit which includes at least one inductance and at least one capacitance.

7. The system of claim 6, wherein the resonant LC oscillator circuit includes:

a first phase output;

a second phase output;

a first inductor coupled between a voltage source and the first phase output;

a second inductor coupled between the voltage source and the second phase output;

a first transistor with a source terminal coupled to a base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output; and

a second transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output.

8. The system of claim 1, wherein the first set of switching devices includes power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

9. The system of claim 1, wherein the first capacitor includes one or more ultra-low-ESR and ultra-low-ESL ceramic capacitors.

10. The system of claim 1, wherein the clocking circuit is configured to run intermittently to balance voltages between the first bank and the second bank.

11. The system of claim 1, wherein the clocking circuit is configured to run continuously to maintain balanced voltages between the first bank and the second bank.

12. A battery pack that balances voltages between battery banks, comprising:

a plurality of battery banks, including a first bank and a second bank, wherein the plurality of battery banks are electrically coupled in series, wherein each battery bank includes one or more battery cells, wherein if a battery bank comprises multiple battery cells, the multiple battery cells are electrically coupled in parallel;

a first capacitor with a first terminal and a second terminal;

a second capacitor with a first terminal and a second terminal;

a first set of switching devices which selectively couple the first and second terminals of the first capacitor to first and second terminals of the first bank, and first and second terminals of the second bank; and

a second set of switching devices which selectively couple the first and second terminals of the second capacitor to the first and second terminals of the first bank, and the first and second terminals of the second bank; and

a clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase;

wherein the clocking circuit is configured to;

control the first set of switching devices, so that during the first phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the first bank, respectively, and during the second phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the second bank, respectively; and

control the second set of switching devices, so that during the first phase the first and second terminals of the second capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the second capacitor are coupled to the first and second terminals of the first bank, respectively.

13. The battery pack of claim 12,

wherein the plurality of banks also includes a third bank which is electrically coupled in series with the first bank and the second bank;

wherein the system additionally comprises a third capacitor with a first terminal and a second terminal; and

wherein the first set of switching devices and the clocking circuit are configured so that during the first phase the first and second terminals of the third capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the third capacitor are coupled to the first and second terminals of the third bank, respectively.

14. The battery pack of claim 12, wherein the clocking circuit is a resonant LC oscillator circuit which includes at least one inductance and at least one capacitance.

15. A method for balancing voltages between a plurality of battery banks, including a first bank and a second bank which are electrically coupled in series, the method comprising:

using a clocking circuit to generate clock signals with substantially non-overlapping clock phases, including a first phase and a second phase; and

applying the clock signals to a first set of switching devices so that during the first phase, the first and second terminals of a first capacitor are coupled to the first and second terminals of the first bank, respectively, and during the second phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the second bank, respectively;

wherein applying the clock signal includes applying the clock signal to a second set of switching devices, so that during the first phase the first and second terminals of a second capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the second capacitor are coupled to the first and second terminals of the first bank, respectively.

16. The method of claim 15,

wherein the plurality of banks also includes a third bank which is electrically coupled in series with the first bank and the second bank;

and

wherein applying the clock signals to a first set of switching devices includes ensuring that during the first phase first and second terminals of a third capacitor are coupled to the first and second terminals of the second bank, respectively, and during the second phase the first and second terminals of the third capacitor are coupled to the first and second terminals of the third bank, respectively.

17. The method of claim 15, wherein using the clocking circuit includes using a resonant LC oscillator circuit which includes at least one inductance and at least one capacitance.

18. The method of claim 15, wherein using the clocking circuit to generate clock signals includes intermittently running the clock circuit to balance voltages between the first bank and the second bank.

19. The method of claim 15, wherein using the clocking circuit to generate clock signals includes continuously running the clock circuit to maintain balanced voltages between the first bank and the second bank.