BASE STATION APPARATUS AND RESOURCE ALLOCATION METHOD

• US 20150124751A1
• Filed: 12/23/2014
• Published: 05/07/2015
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Sun Patent Trust
• Original Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Inventors: Takaoka, Shinsuke, Nakao, Seigo, Imamura, Daichi, Hoshino, Masayuki
• Granted Patent: US 9,173,220 B2
• Time in Patent Office: Days
• US Class Current: 370/329
• CPC Class Codes: H04B 7/0456 Selection of precoding matrices or codebooks, e.g. using matrices antenna weighting
• CPC Class Codes: H04J 13/0059 CAZAC [constant-amplitude and zero auto-correlation]
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453
• CPC Class Codes: H04L 27/2636 with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
• CPC Class Codes: H04L 5/0007 the frequencies being orthogonal, e.g. OFDM(A), DMT
• CPC Class Codes: H04L 5/0021 in which codes are applied as a frequency-domain sequences, e.g. MC-CDMA
• CPC Class Codes: H04L 5/0023 Time-frequency-space
• CPC Class Codes: H04L 5/0041 Frequency-non-contiguous
• CPC Class Codes: H04L 5/0046 Determination of how many bits are transmitted on different sub-channels
• CPC Class Codes: H04L 5/006 Quality of the received signal, e.g. BER, SNR, water filling
• CPC Class Codes: H04W 72/0453 Resources in frequency domain, e.g. a carrier in FDMA
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A wireless communication terminal apparatus wherein even when a SC-FDMA signal is divided into a plurality of clusters and the plurality of clusters are then mapped to respective discontinuous frequency bands (when C-SC-FDMA is used), the improvement effect of system throughput can be maintained, while the user throughput can be improved. In the apparatus, a DFT unit (210) subjects a symbol sequence of time domain to a DFT process, thereby generating signals of frequency domain. A setting unit (211) divides the signals input from the DFT unit (210) into a plurality of clusters according to a cluster pattern that is in accordance with an MCS set, an encoding size, or the number of Ranks occurring during MIMO transmissions, which is indicated in those signal input, and then maps the plurality of clusters to the respective ones of a plurality of discontinuous frequency resources, thereby setting a constellation of the plurality of clusters in the frequency domain.

Claims

1. An integrated circuit for controlling a process comprising:

performing discrete Fourier transformations (DFT) on a plurality of symbol sequences, each symbol sequence corresponding to one of a plurality of layers;

multiplying the plurality of DFT performed symbol sequences by a precoding matrix, generating a plurality of precoded symbol sequences; and

mapping each of the plurality of precoded symbol sequences on a same set of discontinuous frequency resources, each frequency resource being located on a separate position from other frequency resources on a frequency axis, wherein the same set of discontinuous frequency resources means that a first set of discontinuous frequency resources to which a first precoded symbol sequence is mapped, and a second set of discontinuous frequency resources to which a second precoded symbol sequence is mapped share;

a number of clusters used to map each precoded symbol sequence;

a cluster size, the cluster size being a discontinuous frequency resource bandwidth; and

a frequency position of each cluster.

2. The integrated circuit according to claim 1, comprising:

circuitry, which in operation, controls the process; and

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 2 wherein the cluster size is defined according to a minimum cluster size that is common among the plurality of layers.

4. The integrated circuit according to claim 2 wherein a rank indicator indicating a number of layers is equal to or less than a number of antennas provided at a terminal apparatus.

5. The integrated circuit according to claim 2 wherein the plurality of symbol sequences are code words different from each other.

6. The integrated circuit according to claim 2 wherein a number of layers is equal to a number of codewords.

7. An integrated circuit for controlling a process comprising:

determining a resource allocation to map each of a plurality of precoded symbol sequences to a plurality of frequency resources, each of the plurality of frequency resources being located on a separate position from other frequency resources on a frequency axis, wherein the plurality of precoded symbol sequences are generated at a terminal apparatus by multiplying a plurality of symbol sequences by a precoding matrix, each symbol sequence corresponding to one of a plurality of layers, wherein a first plurality of frequency resources to which a first precoded symbol sequence is mapped, and a second plurality of frequency resources to which a second precoded symbol sequence is mapped share;

a number of clusters used to map each precoded symbol sequence;

a cluster size, the cluster size being a discontinuous frequency resource bandwidth; and

a frequency position of each cluster; and

notifying the terminal apparatus of information indicating the determined resource allocation.

8. The integrated circuit according to claim 7, comprising:

circuitry, which in operation, controls the process; and

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.

9. The integrated circuit according to claim 8, the process comprising:

receiving a signal including the plurality of precoded symbol sequences which are mapped to the plurality of frequency resources; and

combining the plurality of frequency resources to generate symbol sequences.

10. The integrated circuit according to claim 8 wherein the cluster size is defined according to a minimum cluster size that is common among the plurality of layers.

11. The integrated circuit according to claim 8 wherein a rank index indicating a number of layers is equal to or less than a number of antennas provided at the terminal apparatus. 12 The integrated circuit according to claim 8 wherein the plurality of symbol sequences are code words different from each other.

13. The integrated circuit according to claim 8 wherein a number of layers is equal to a number of codewords.

14. The integrated circuit according to claim 8 wherein when a number of codewords is smaller than a number of layers, a part of the plurality of precoded symbol sequences derive from a plurality of symbol sequences corresponding to a same codeword.

15. The integrated circuit according to claim 8 wherein when a plurality of codewords are used, the plurality of precoded symbol sequences derives from a plurality of first symbol sequences corresponding to a first codeword and a plurality of second symbol sequences corresponding to a second codeword which is different from the first codeword.

16. The integrated circuit according to claim 15 wherein a number of layers corresponding to the first codeword is equal to a number of layers corresponding to the second codeword.

17. An integrated circuit, comprising circuitry, which, in operation:

performs discrete Fourier transformations (DFT) on a plurality of symbol sequences, each symbol sequence corresponding to one of a plurality of layers;

multiplies the plurality of DFT performed symbol sequences by a precoding matrix, generating a plurality of precoded symbol sequences; and

maps each of the plurality of precoded symbol sequences on a same set of discontinuous frequency resources, each frequency resource being located on a separate position from other frequency resources on a frequency axis, wherein the same set of discontinuous frequency resources means that a first set of discontinuous frequency resources to which a first precoded symbol sequence is mapped, and a second set of discontinuous frequency resources to which a second precoded symbol sequence is mapped share;

a number of clusters used to map each precoded symbol sequence;

a cluster size, the cluster size being a discontinuous frequency resource bandwidth; and

a frequency position of each cluster.

18. The integrated circuit according to claim 17, comprising:

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.

19. An integrated circuit, comprising circuitry, which, in operation:

determines a resource allocation to map each of a plurality of precoded symbol sequences to a plurality of frequency resources, each of the plurality of frequency resources being located on a separate position from other frequency resources on a frequency axis, wherein the plurality of precoded symbol sequences are generated at a terminal apparatus by multiplying a plurality of symbol sequences by a precoding matrix, each symbol sequence corresponding to one of a plurality of layers, wherein a first plurality of frequency resources to which a first precoded symbol sequence is mapped, and a second plurality of frequency resources to which a second precoded symbol sequence is mapped share;

a number of clusters used to map each precoded symbol sequence;

a cluster size, the cluster size being a discontinuous frequency resource bandwidth; and

a frequency position of each cluster; and

notifies the terminal apparatus of information indicating the determined resource allocation.

20. An integrated circuit according to claim 19, comprising:

at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data.