APPARATUS AND METHOD OF THREE DIMENSIONAL CONDUCTIVE LINES

• US 20150130068A1
• Filed: 11/12/2013
• Published: 05/14/2015
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Chih-Yu, LIN, Kao-Cheng, WANG, Li-Wen, CHEN, Yen-Huei
• Granted Patent: US 9,524,920 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Claims

1. An inter-tier memory column, comprising:

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), the first segment comprising a first bit line, a first bit line bar, and a first plurality of memory cells, said first plurality of memory cells disposed between and connected to said first bit line and said first bit line bar;

a second segment disposed within a second tier of the 3D IC, comprising a second bit line, a second bit line bar, and a second plurality of memory cells, said second plurality of memory cells disposed between and connected to said second bit line and said second bit line bar; and

wherein said first bit line is connected to said second bit line, and said first bit line bar is connected to said second bit line bar.

2. The inter-tier memory column of claim 1, wherein said first segment and said second segment are aligned parallel to each other.

3. The inter-tier memory column of claim 1, further comprising:

an inter-tier word line connected across said first segment and said second segment.

4. The inter-tier memory column of claim 1,

wherein said first bit line comprises a first bit line part and a horizontally offset second bit line part, said second bit line comprises a third bit line part and a horizontally offset fourth bit line part;

and

wherein said horizontally offset second bit line part and said horizontally offset fourth bit line part are connected by a vertical bit line.

5. The inter-tier memory column of claim 4,

wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a horizontally offset fourth bit line bar part;

and

wherein said horizontally offset second bit line bar part and said horizontally offset fourth bit line bar part are connected by a vertical bit line.

6. The inter-tier memory column of claim 1, wherein said first bit line and said second bit line bar are disposed on a first side of the first and second pluralities of memory cells and said second bit line and said first bit line bar are disposed on a second side of the first and second pluralities of memory cells.

7. The inter-tier memory column of claim 6,

wherein said first bit line comprises a first bit line part and a horizontally offset second bit line part, said second bit line comprises a third bit line part and a perpendicular fourth bit line part;

and

wherein said horizontally offset second bit line part and said perpendicular fourth bit line part are connected by a vertical bit line.

8. The inter-tier memory column of claim 7,

wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a perpendicular fourth bit line bar part;

and

wherein said horizontally offset second bit line bar part and said perpendicular fourth bit line bar part are connected by a vertical bit line.

9. A three-dimensional integrated circuit (3D IC) comprising:

a first memory cell segment and a second memory cell segment, disposed within a first tier of the 3D IC;

a third memory cell segment and a fourth memory cell segment, disposed within a second tier of the 3D IC;

an inter-tier conductive line connected between at least one segment in the first tier and at least one segment in the second tier; and

wherein each memory cell segment comprises a first bit line, a second bit line, and at least one memory cell disposed between and connected to said first bit line and said second bit line.

10. The 3D IC of claim 9, wherein the inter-tier conductive line is a word line.

11. The 3D IC of claim 9, wherein the inter-tier conductive line is a bit line formed by connecting the first and second bit lines of the first memory cell segment with respective bit lines of the fourth memory cell segment.

12. The 3D IC of claim 11 wherein the first and second bit lines of the second memory cell segment are connected with respective bit lines of the third memory cell segment.

13. The 3D IC of claim 12, further comprising:

a fifth memory cell segment and a sixth memory cell segment, disposed within a third tier of the 3D IC;

wherein the fifth memory cell segment is connected to the first memory cell segment and the third memory cell segment, and the sixth memory cell segment is connected to the second memory cell segment and the fourth memory cell segment.

14. The 3D IC of claim 12, wherein each bit line is aligned parallel to a first longitudinal axis and wherein the first bit line of said first memory cell segment is disposed on a first side of first longitudinal axis and is connected to first bit line of said fourth memory cell segment which is disposed on a second side of first longitudinal axis.

15. The 3D IC of claim 14, wherein the first bit line bar of said first memory cell segment is disposed on a second side of first longitudinal axis and is connected to first bit line bar of said fourth memory cell segment which is disposed on a first side of first longitudinal axis.

16. (canceled)

17. (canceled)

18. (canceled)

19. (canceled)

20. (canceled)

21. A three-dimensional integrated circuit (3D IC) comprising:

a first memory cell segment and a second memory cell segment, disposed within a first tier of the 3D IC;

a third memory cell segment and a fourth memory cell segment, disposed within a second tier of the 3D IC;

wherein each memory cell segment comprises a first bit line, a second bit line, and at least one memory cell disposed between and connected to said first bit line and said second bit line; and

wherein each of said first bit lines are aligned parallel to and disposed on a first side of a first longitudinal axis and each of said second bit lines are aligned parallel to and disposed on a second side of said first longitudinal axis.

22. The 3D IC of claim 21 wherein the first bit line and second bit line of said first memory cell segment are connected to the first bit line and second bit line of said fourth memory cell segment.

23. The 3D IC of claim 22 wherein the first bit line and second bit line of said second memory cell segment are connected to the first bit line and second bit line of said third memory cell segment.

24. The 3D IC of claim 23 wherein an inter-tier word line is connected across a memory cell segment disposed within the first tier and a memory cell segment disposed within the second tier.

25. The 3D IC of claim 24 wherein each of said first, second, third, and fourth memory cell segments comprises a plurality of memory cells disposed between and connected to the respective first bit line and second bit line.