HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT
First Claim
Patent Images
1. A memory module comprising:
- a plurality of device sites; and
a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links.
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Abstract
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
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Citations
28 Claims
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1. A memory module comprising:
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a plurality of device sites; and a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method comprising:
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operating a memory module in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links; and operating the memory module in a second mode when the memory module is inserted onto a second type of memory channel with multi-drop data-links. - View Dependent Claims (22, 23, 24)
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25. A printed circuit board (PCB) comprising:
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a plurality of pins; a plurality of memory devices; a command and address (CA) buffer component coupled to the plurality of memory devices; and a plurality of data (DQ) buffer components coupled to the plurality of memory devices, wherein a first DQ buffer component comprises; a plurality of primary ports coupled to the plurality of pins; a plurality of secondary ports coupled to the plurality of memory devices; and a plurality of bi-directional paths between the plurality of primary ports and the plurality of secondary ports, wherein the first DQ buffer component is programmed to operate the plurality of bi-directional paths in a first configuration when the PCB is inserted onto a first type of memory channel with multi-drop data-links and in a second configuration when the PCB is inserted onto a second type of memory channel with point-to-point data-links. - View Dependent Claims (26, 27, 28)
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Specification