LEVERAGING CHIP VARIABILITY

• US 20150135028A1
• Filed: 01/23/2015
• Published: 05/14/2015
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Zorn, Benjamin, Bittner, Ray, Kirovski, Darko, Pattabiraman, Karthik
• Granted Patent: US 9,666,303 B2
• Time in Patent Office: Days
• US Class Current: 714/723
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Claims

1. A chip comprising:

a region-specific error profile able to indicate reliability traits of respective regions of the chip according to a given operating value;

the region-specific error profile being used to obtain indications of respective reliabilities of the regions, respectively at a target operating value; and

a set of the regions selected based on the indications of the respective reliabilities; and

the selected set of regions being made available or unavailable.

2. A chip according to claim 1, wherein the region-specific error profile was derived by measuring errors on the chip that occur at different levels of an error-sensitive factor.

3. A chip according to claim 2, wherein the chip comprises cells, and wherein the error-sensitive factor comprises a physical aspect of the chip whose variation directly affects the probability that the cells of the chip will incorrectly store values.

4. A chip according to claim 3, wherein the error-sensitive factor comprises temperature, power, clock rate, or voltage.

5. A chip according to claim 1, wherein the set of regions is made unavailable by a memory controller of an operating system executing on a computing device that comprises the chip.

6. A chip according to claim 5, wherein the rate of power consumption of the chip is reduced in association with making the regions unavailable.

7. A chip according to claim 6, wherein the rate of power consumption is reduced by altering a refresh rate or voltage of the chip.

8. A method of using a chip for storing data, the method comprising:

obtaining a first target value of an operating factor of the chip, the chip comprising regions, the operating factor comprising a variable physical property of the chip;

providing the first target value to a reliability map, the reliability map providing, according to the first target value, first indications of reliability of the respective regions;

preforming a first region adjustment comprising adjusting which of the regions are available for storing data based on the first indications of reliability;

obtaining a second target value of the operating factor of the chip, and providing the second target value to the reliability map, the reliability map providing, according to the second target value, second indications of reliability of the respective regions; and

performing a second region adjustment comprising adjusting which of the regions are available for storing data based on the second indications of reliability.

9. A method according to claim 8, wherein the second region adjustment is performed after the first region adjustment, and wherein the method further comprises:

supplying power to the chip according to the first target value during a time between the first region adjustment and the second region adjustment; and

supplying power to the chip according to the second target value during a time after the second region adjustment.

10. A method according to claim 8, wherein the first target value and the second target value comprise respective sensed measurements of the physical property of the chip.

11. A method according to claim 8, wherein the first region adjustment reduces a number of regions available for storing data, and wherein the second region adjustment increases the number of regions available for storing data.

12. A method according to claim 8, wherein the first region adjustment and the second region adjustment are performed by an operating system controlling use of the chip.

13. A method according to claim 12, wherein the first region adjustment and the second region adjustment affect an amount of physical memory available to be allocated by the operating system.

14. A method according to claim 13, wherein the first operating value is obtained responsive to a determination by the operating system that the amount of physical memory available to be allocated is sufficiently high or that an amount of physical memory in use is sufficiently low, and wherein the first operating value corresponds to lower power consumption by the chip.

15. An apparatus comprising:

a chip;

a region-specific error profile stored by the apparatus, the region-specific error profile, when the apparatus is operating, able to indicate reliabilities of respective regions of the chip;

a memory controller that, when the apparatus is operating, is able to obtain, from the region-specific error profile, indications of the respective regions, the indications corresponding to respective reliabilities of the regions; and

the memory controller, when the apparatus is operating, able to allocate memory from the regions according to the obtained indications of the respective regions.

16. An apparatus according to claim 15, wherein the region-specific error profile is able to, when the apparatus is operating, indicate, for each region, region-specific reliabilities for respective operating values of an error-specific factor.

17. An apparatus according to claim 15, wherein the memory controller comprises a component of an operating system.

18. An apparatus according to claim 17, wherein the memory controller, when the apparatus is operating, is able to receive allocation requests for memory, the allocation requests indicating respective reliabilities of memory being requested, and wherein the memory controller satisfies the requests based on the indications of the respective regions of the chip.

19. An apparatus according to claim 15, wherein the memory controller comprises a component of the chip.

20. An apparatus according to claim 15, wherein the region-specific error profile was derived by testing the chip at different values of an error-sensitive factor, the error-sensitive factor comprising a factor that correlates with reliability of the chip.