ELECTROLUMINESCENCE DISPLAY DEVICE

• US 20150137132A1
• Filed: 01/05/2015
• Published: 05/21/2015
• Est. Priority Date: 11/19/1999
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ONO, Koji, SUZAWA, Hideomi, ARAO, Tatsuya
• Granted Patent: US 9,673,223 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

Claims

1. (canceled)

2. A display device comprising:

a glass substrate;

a base film over and in contact with the glass substrate; and

a plurality of pixels over the base film,

wherein;

at least one of the plurality of pixels comprises;

a crystalline silicon layer over and in contact with the base film;

a gate insulating film over and in contact with the crystalline silicon layer;

a gate electrode over and in contact with the gate insulating film;

a first insulating film over and in contact with the gate electrode and the gate insulating film;

a source electrode and a drain electrode over the first insulating film, the source electrode and the drain electrode being in contact with the crystalline silicon layer in a contact hole formed in the first insulating film and the gate insulating film; and

a pixel electrode over and in contact with one of the source electrode and the drain electrode;

the crystalline silicon layer is overlapped with a pixel electrode in a neighboring pixel which is adjacent to the one of the plurality of pixels with a gate line interposed therebetween; and

the gate electrode is a part of the gate line.

3. The display device according to claim 2,

wherein the crystalline silicon layer is folded so as to extend between the one of the plurality of pixels and the neighboring pixel.

4. The display device according to claim 2,

wherein the base film comprises a plurality of layers selected from a silicon oxide film and a silicon nitride oxide film.

5. The display device according to claim 2,

wherein:

the gate electrode has a stacked structure comprising a first layer and a second layer;

the first layer comprises an element selected from tungsten, tantalum, titanium, and molybdenum; and

the second layer comprises nitrogen and an element which is selected from tungsten, tantalum, titanium, and molybdenum.

6. The display device according to claim 2,

wherein the gate electrode comprises nitrogen and tantalum.

7. The display device according to claim 2,

wherein the gate electrode has a tapered shape in an end portion.

8. The display device according to claim 2, further comprising a source line,

wherein:

the source electrode is a part of the source line; and

the source line overlaps with a channel formation region of the crystalline silicon layer.

9. The display device according to claim 8,

wherein the source electrode contacts with the crystalline silicon layer under the source line.

10. The display device according to claim 2,

wherein the crystalline silicon layer comprises:

a source region and a drain region which are in contact with the source electrode and the drain electrode, respectively;

a pair of doped regions between the source region and the drain region; and

a channel formation region between the pair of doped regions.

11. The display device according to claim 10,

wherein the source region and the drain region includes an impurity at a concentration higher than a concentration of the impurity in the pair of doped regions.

12. The display device according to claim 10,

wherein a part of the pair of doped regions overlaps with the gate electrode.

13. A display device comprising:

a glass substrate;

a base film over and in contact with the glass substrate;

a gate line over the base film;

a source line overpassing the gate line;

a pixel over the base film and electrically connected to the gate line and the source line; and

a neighboring pixel which is adjacent to the pixel with the gate line interposed therebetween,

wherein;

the pixel comprises;

a crystalline silicon layer over and in contact with the base film;

a gate insulating film over and in contact with the crystalline silicon layer;

a gate electrode, which is a part of the gate line, over and in contact with the gate insulating film;

a first insulating film over and in contact with the gate electrode and the gate insulating film;

a drain electrode and a source electrode, which is a part of the source line, over the first insulating film, the drain electrode and the source electrode being in contact with the crystalline silicon layer in a contact hole formed in the first insulating film and the gate insulating film; and

a pixel electrode over and in contact with one of the source electrode and the drain electrode;

the crystalline silicon layer contacts with the source line under the source line, extends along and under the source line in a first direction from the pixel to the neighboring pixel while crossing the gate line, extends in a second direction so as to overlap with a pixel electrode of the neighboring pixel, extends in a third direction from the neighboring pixel to the pixel while crossing the gate line, and then contacts with the drain electrode.

14. The display device according to claim 13,

wherein the base film comprises a plurality of layers selected from a silicon oxide film and a silicon nitride oxide film.

15. The display device according to claim 13,

wherein:

the gate electrode has a stacked structure comprising a first layer and a second layer;

the first layer comprises an element selected from tungsten, tantalum, titanium, and molybdenum; and

the second layer comprises nitrogen and an element which is selected from tungsten, tantalum, titanium, and molybdenum.

16. The display device according to claim 13,

wherein the gate electrode comprises nitrogen and tantalum.

17. The display device according to claim 13,

wherein the gate electrode has a tapered shape in an end portion.

18. The display device according to claim 13,

wherein:

the source line overlaps with a channel formation region of the crystalline silicon layer.

19. The display device according to claim 13,

wherein the crystalline silicon layer comprises:

a source region and a drain region which are in contact with the source electrode and the drain electrode, respectively;

a pair of doped regions between the source region and the drain region; and

a channel formation region between the pair of doped regions.

20. The display device according to claim 19,

wherein the source region and the drain region includes an impurity at a concentration higher than a concentration of the impurity in the pair of doped regions.

21. The display device according to claim 19,

wherein a part of the pair of doped regions overlaps with the gate electrode.