TSV Structures and Methods for Forming the Same

• US 20150137360A1
• Filed: 01/28/2015
• Published: 05/21/2015
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yung-Chi, Chen, Hsin-Yu, Chiou, Wen-Chih, Yang, Ku-Feng, Wu, Tsang-Jiuh, Lin, Jing-Cheng
• Granted Patent: US 9,373,575 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11011 Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1405 Shape
• CPC Class Codes: H01L 2224/14104 relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/067 : Polyphenylene
• CPC Class Codes: H01L 2924/0705 : Sulfur containing polymer
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Claims

1. A device comprising:

a substrate;

a conductive feature extending through the substrate, wherein the conductive feature comprises;

a conductive pad extending past a first surface of the substrate, wherein the conductive pad comprises a substantially planar top surface; and

a conductive bump contacting the conductive pad, wherein the conductive bump comprises a non-planar top surface over the substantially planar top surface, and wherein the conductive bump and the conductive pad are formed of a same material.

2. The device of claim 1, wherein the non-planar top surface of the conductive bump is rounded.

3. The device of claim 1, wherein no interface is formed between the conductive bump and the conductive pad.

4. The device of claim 1, wherein the conductive bump is aligned with a portion of the conductive feature in the substrate.

5. The device of claim 1, wherein the substantially planar top surface is aligned to a portion of the substrate encircling the conductive feature.

6. The device of claim 1 further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad, wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump, and a second portion over and in contact with the substantially planar top surface of the conductive pad.

7. The device of claim 1 further comprising a solder region over the conductive pad and the conductive bump, wherein the solder region comprises a first bottom surface that is not planar, and a second bottom surface that is substantially planar.

8. The device of claim 1 further comprising a passivation layer, wherein the passivation layer comprises portions covering edge portions of the conductive pad.

9. The device of claim 8 further comprising a stress buffer layer over the passivation layer, wherein the stress buffer layer comprises portions covering the edge portions of the conductive pad.

10. The device of claim 9, further comprising a solder region over the conductive pad and the conductive bump, wherein the stress buffer layer is underlying and aligned to the solder region, and wherein the stress buffer layer does not extend beyond the solder region.

11. A device comprising:

a semiconductor substrate;

a through-via extending through the semiconductor substrate; and

a metal connector on a first side of the semiconductor substrate and over the through-via, wherein a surface of the metal connector comprises;

a substantially planar portion; and

a non-planar portion extending over the substantially planar portion.

12. The device of claim 11, wherein the metal connector and the through-via are formed of a same material, and wherein no visible interface is formed between the through-via and the metal connector.

13. The device of claim 11, further comprising:

a nickel-containing layer in contact with the metal connector, wherein the nickel-containing layer comprises a non-planar portion aligned to the through-via, and a planar portion not aligned to the through-via; and

a solder region over the nickel-containing layer, wherein the solder region comprises a non-planar bottom surface portion aligned to the through-via, and a planar bottom surface portion not aligned to the through-via.

14. The device of claim 13, further comprising stress buffer layer disposed between the nickel-containing layer and the metal connector.

15. The device of claim 14, wherein the stress buffer layer is only disposed under the solder region.

16. A device comprising:

a substrate comprising an integrated circuit device at a first side;

a first conductive feature extending from the first side of the substrate past a second side of the substrate opposite the first side of the substrate, and wherein a portion of the conductive feature extending past the second side of the substrate comprises;

a substantially planar first surface; and

a non-planar second surface connected to the first surface;

a second conductive feature over and contacting the first conductive feature; and

a solder region over and contacting the second conductive feature.

17. The device of claim 16, wherein the first and the second conductive features are formed of different materials.

18. The device of claim 16 further comprising a passivation layer covering edge portions of the first conductive feature.

19. The device of claim 18 further comprising a stress buffer layer over the passivation layer, wherein the stress buffer layer is disposed between the second conductive feature and the passivation layer.

20. The device of claim 16, wherein the non-planar second surface of the first conductive feature is higher than the substantially planar first surface by greater than about 0.1 μ

m.