Through Silicon Via Structure and Method

• US 20150137361A1
• Filed: 01/29/2015
• Published: 05/21/2015
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jeng, Shin-Puu, Chiou, Wen-Chih, Tsai, Fang Wen, Tsai, Chen-Yu
• Granted Patent: US 9,299,676 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05559 : non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 : On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05568 : the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16113 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Claims

1. A semiconductor device comprising:

a through silicon via protruding from a substrate, the through silicon via having a sidewall;

a liner extending along the sidewall away from the substrate, the liner terminating prior to reaching a top surface of the through silicon via;

a passivation layer comprising a first upper surface a first distance away from the substrate and a second upper surface a second distance away from the substrate, the second distance being greater than the first distance, the second upper surface being adjacent to the liner;

a conductive material over and in physical contact with the sidewall and the top surface of the through silicon via; and

a first external device in electrical connection with the through silicon via through the conductive material.

2. The semiconductor device of claim 1, wherein the first external device is a semiconductor die.

3. The semiconductor device of claim 2, wherein the semiconductor die is bonded in a flip chip configuration.

4. The semiconductor device of claim 2, wherein the first external device is in electrical connection with the through silicon via and a second through silicon via through the conductive material.

5. The semiconductor device of claim 1, further comprising a second passivation layer at least partially covering the conductive material.

6. The semiconductor device of claim 1, further comprising a second external device bonded in electrical connection with the through silicon via, wherein the second external device is located on an opposite side of the substrate from the first external device.

7. A semiconductor device comprising:

a through silicon via protruding from a substrate, the through silicon via having a sidewall;

a first external device electrically connected to the through silicon via;

a metallization layer located on an opposite side of the substrate than the first external device;

a liner extending along the sidewall away from the substrate, the liner terminating prior to reaching a top surface of the through silicon via;

a passivation layer comprising a first upper surface a first distance away from the substrate and a second upper surface a second distance away from the substrate, the second distance being greater than the first distance, the second upper surface being adjacent to the liner;

a conductive material over and in physical contact with the sidewall and the top surface of the through silicon via, wherein the first external device is electrically connected to the through silicon via through the conductive material; and

a second external device located on an opposite side of the metallization layer than the first external device, the second external device being electrically connected to the metallization layer.

8. The semiconductor device of claim 7, further comprising a second passivation layer at least partially covering a sidewall of the conductive material.

9. The semiconductor device of claim 8, further comprising:

an opening through the second passivation layer; and

a conductive connection extending through the opening, wherein the first external device is electrically connected to the through silicon via through the conductive connection.

10. The semiconductor device of claim 9, wherein the conductive connection comprises a conductive bump.

11. The semiconductor device of claim 7, wherein the first external device is bonded in a flip chip configuration.

12. The semiconductor device of claim 7, wherein the second external device is a printed circuit board.

13. The semiconductor device of claim 7, wherein the first external device is electrically connected to the through silicon via and a second through silicon via through the conductive material.

14. The semiconductor device of claim 7, wherein the first external device is a first semiconductor die and the second external device is a second semiconductor die.

15. A semiconductor device comprising:

a through silicon via in a substrate, the through silicon via comprising sidewalls, wherein the through silicon via extends through a metallization layer;

a dielectric liner adjacent to the sidewalls;

a dielectric layer over the substrate and adjacent to the dielectric liner, the dielectric layer having two different thicknesses, wherein the sidewall extends further from the substrate than the dielectric layer; and

a conductive material in contact with the sidewalls of the through silicon via.

16. The semiconductor device of claim 15, further comprising a passivation layer at least partially covering a sidewall of the conductive material.

17. The semiconductor device of claim 16, further comprising a conductive connection extending through the passivation layer to make physical contact with the conductive material.

18. The semiconductor device of claim 17, wherein the conductive connection is a conductive bump.

19. The semiconductor device of claim 17, further comprising a first external device in electrical connection with the through silicon via through the conductive material.

20. The semiconductor device of claim 19, further comprising a second external device in electrical connection with the metallization layer, wherein the second external device and the metallization layer are located on a same side of the substrate.