METHOD OF FABRICATING A GATE DIELECTRIC LAYER

• US 20150140765A1
• Filed: 12/30/2014
• Published: 05/21/2015
• Est. Priority Date: 04/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Wei-Yang, YU, Xiong-Fei, LEE, Da-Yuan, HSU, Kuang-Yuan
• Granted Patent: US 9,263,546 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.

Claims

1. A method of making a semiconductor device, the method comprising:

forming an active region in a substrate;

forming a first gate structure over the active region, wherein forming the first gate structure comprises;

forming a first interfacial layer, wherein an entirety of a top surface of the first interfacial layer is a curved convex surface;

forming a first high-k dielectric over the first interfacial layer; and

forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.

2. The method of claim 1, wherein forming the first interfacial layer comprises using silicon oxide or silicon oxynitride.

3. The method of claim 1, further comprising converting the first interfacial layer into a second interfacial layer using a fluorine-containing plasma treatment, wherein a thickness of the second interfacial layer is greater than the thickness of the first interfacial layer.

4. The method of claim 3, wherein converting the first interfacial layer into the second interfacial layer using the fluorine-containing plasma treatment comprises a ratio of a maximum thickness of the first interfacial layer to a maximum thickness of the second interfacial layer ranges from 5/9 to 3/5.

5. The method of claim 3, wherein performing the fluorine-containing plasma treatment on the high-k dielectric and the first interfacial layer comprises concentrating the high-k dielectric and the second interfacial layer with a fluorine-dopant, wherein the concentration of the fluorine-dopant ranges from 2% to 8% in terms of atomic percent.

6. The method of claim 3, wherein using the fluorine-containing plasma treatment comprises using a chemical selected from NF₃, CF₄, or SF₆ as a fluorine source gas.

7. The method of claim 3, wherein the fluorine-containing plasma treatment is performed under a pressure of ranging from 50 mTorr to 100 mTorr.

8. A method of making a semiconductor device, the method comprising:

forming an active region in a substrate; and

depositing a gate structure over the active region, wherein forming the gate structure comprises;

depositing a first interfacial layer;

depositing a high-k dielectric over the first interfacial layer, wherein an entirety of a top surface of the first interfacial layer is a curved convex surface; and

depositing a gate electrode over a first portion of the high-k dielectric and surrounded by a second portion of the high-k dielectric.

9. The method of claim 8, further comprising converting the first interfacial layer into a second interfacial layer using a fluorine-containing plasma treatment

10. The method of claim 9, wherein converting the first interfacial layer into the second interfacial layer comprises a thickness of the second interfacial layer ranges from 1.5 nm to 2.5 nm.

11. The method of claim 9, wherein converting the first interfacial layer into the second interfacial layer comprises a thickness of the second interfacial layer is greater than the thickness of the first interfacial layer.

13. The method of claim 9, wherein using the fluorine-containing plasma treatment comprises using a chemical selected from NF₃, CF₄, or SF₆ as a fluorine source gas.

14. The method of claim 9, wherein the fluorine-containing plasma treatment is performed under a temperature of ranging from 100°

C. to 350°

C.

15. The method of claim 9, wherein the fluorine-containing plasma treatment is performed under a source power of ranging from 500 to 3000 W.

16. A method for fabricating a gate dielectric layer, comprising:

forming an interfacial layer over a substrate;

forming a high-k dielectric on the interfacial layer; and

performing a fluorine-containing plasma treatment on the high-k dielectric and interfacial layer.

17. The method of claim 16, wherein performing the fluorine-containing plasma treatment is performed using a chemical selected from NF₃, CF₄, or SF₆ as a fluorine source gas.

18. The method of claim 16, wherein performing the fluorine-containing plasma treatment is performed under a pressure of about 50 mTorr to 100 mTorr.

19. The method of claim 16, wherein performing the fluorine-containing plasma treatment is performed at a temperature of about 100°

C. to about 350°

C.

20. The method of claim 16, wherein performing the fluorine-containing plasma treatment is performed under a source power of about 500 to 3000 W.