VECTOR CHECKSUM INSTRUCTION
First Claim
Patent Images
1. A method of executing a machine instruction in a central processing unit, the method comprising:
- obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;
at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation;
a first register field to be used to designate a first register, the first register comprising a first operand;
a second register field to be used to designate a second register, the second register comprising a second operand; and
executing the machine instruction, the executing comprising;
adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations;
based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and
placing the first result in the selected element of the first operand.
1 Assignment
0 Petitions
Accused Products
Abstract
Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
22 Citations
9 Claims
-
1. A method of executing a machine instruction in a central processing unit, the method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising; at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the machine instruction, the executing comprising; adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
Specification