PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY

• US 20150146494A1
• Filed: 05/22/2014
• Published: 05/28/2015
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Riho, Yoshiro
• Granted Patent: US 10,020,045 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2^N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2^N cells for both normal and self refresh operation modes.

Claims

1. A device comprising:

a plurality of memory cells; and

a controller controlling storage of data in the plurality of memory cells, the controller configured to operate a first access mode which stores one bit data into 1 cell of the memory cells, and a second access mode which stores one bit data into 2^N cells of the memory cells, wherein N is a natural number.

2. The device of claim 1, wherein the first access mode is associated with a normal operation mode.

3. The device of claim 1, wherein the second access mode is associated with a self refresh operation mode.

4. The device of claim 1, wherein the controller is configured to operate in the first access mode which activates a word line to access the one bit data and in the second access mode which activates 2^N word lines to access the one bit data.

5. The device of claim 1, wherein the controller is configured in a first partial access mode to operate the first access mode in a normal operation mode and the second access mode in a self refresh operation mode, and further configured in a second partial access mode to operate the second access mode in both the normal operation mode and the self refresh operation mode.

6. The device of claim 5, wherein the controller is configured in a third partial access mode to operate the first partial access mode in both the normal operation mode and the self refresh operation mode.

7. The device of claim 1, wherein the controller storing causes the power consumption of the device to be a first reduced amount for the first access mode, and causes the power consumption of the device to a second reduced amount for the second access mode, the second reduced amount less than the first reduced amount.

8. A device comprising:

a plurality of memory cells; and

a controller controlling storage of data in the plurality of memory cells, the controller configured to store data in the plurality of memory cells as 1 data bit/cell for a normal operation mode and store data in the plurality of memory cells as 1 data bit/2^N cells for a self refresh operation mode in a first partial access mode, and further configured to store data in the plurality of memory cells as 1 data bit/2^N cells for both a normal operation mode and a self refresh operation mode in a second partial access mode.

9. The device of claim 8, further comprising an address decoder coupled to the controller and configured to select wordlines coupled to the plurality of memory cells to store the data in the plurality of memory cells.

10. The device of claim 9 wherein the address decoder is configured to handle bits of a row address as “

don'"'"'t care”

according to the first or second partial access mode.

11. The device of claim 8, wherein the plurality of memory cells are included in memories of a memory module.

12. A method for managing storage of data in a device, the method comprising:

storing one bit data into 1 cell of the memory cells when operating in a first access mode; and

storing one bit data into 2^N cells of the memory cells when operating in a second access mode, wherein N is a natural number.

13. The method of claim 12, wherein storing one bit data into 2^N cells of the memory cells comprises copying a portion of the one bit data into 2^N cells of the device.

14. The method of claim 12, further comprising:

performing an all bank refresh operation responsive to a partial access mode exit operation; and

storing one bit data into 1 cell of the memory cells.

15. The method of claim 14, wherein the all bank refresh operation responsive to the partial access mode exit operation corresponds to exiting a waiting call state.

16. The method of claim 14, further comprising entering the partial access mode responsive to a partial access mode entry operation corresponding to entering the waiting call state.

17. The device of claim 12, wherein storing one bit data into 1 cell of the memory cells comprises activating a word line and wherein storing one bit data into 2^N cells of the memory cells comprises activating 2^N N word lines.

18. The device of claim 12, wherein storing the one bit data into 1 cell of the memory cells is associated with a normal refresh operation and wherein storing the one bit data into 2^N cells of the memory cells is associated with a self refresh operation.

19. The device of claim 12, wherein storing the one bit data into 2^N cells of the memory cells is associated with both a normal refresh operation and a self refresh operation.