DYNAMIC VOLTAGE-FREQUENCY SCALING TO LIMIT POWER TRANSIENTS

• US 20150153805A1
• Filed: 12/02/2013
• Published: 06/04/2015
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Xu, Shuang
• Granted Patent: US 10,466,763 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clocked electronic device includes first and second control systems. The first control system is configured to decrease clock frequency in the device in response to decreasing supply voltage. The second control system is responsive to clock lag in the device and to an amount of current drawn through the device. It is configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold.

Claims

1. A clocked electronic device comprising:

a first control system configured to decrease clock frequency in the device in response to decreasing supply voltage; and

a second control system responsive to clock lag in the device and to an amount of current drawn through the device, the second control system configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold.

2. The device of claim 1 wherein the second control system is configured to decrease the supply voltage to a point at which instantaneous power dissipation in the device is below an electronic design power (EDP) threshold.

3. The device of claim 2 wherein the operational threshold is equal to the EDP threshold divided by a target supply voltage for the device.

4. The device of claim 2 wherein the second control system is configured to decrease the supply voltage in response to increasing current subject to a load line on which the instantaneous power dissipation in the device approaches the EDP threshold.

5. The device of claim 4 wherein the load line extends, in current space, from the operational threshold to an instantaneous over-current protection rating of the device.

6. The device of claim 2 wherein the second control system includes a division component configured to divide the EDP threshold by the current to compute a load-line voltage.

7. The device of claim 6 wherein the second control system includes a selection component configured to select a smaller of the load-line voltage and a target supply voltage of the device, and to pass the selected voltage to downstream componentry of the second control system, which regulates the supply voltage at the selected voltage level.

8. The device of claim 1 wherein the second control system is configured to further decrease the supply voltage when the current exceeds an instantaneous over-current protection (OCP) rating of the device.

9. The device of claim 1 wherein the second control system is configured to increase the supply voltage in response to increasing clock lag over a first time domain, but to decrease the supply voltage over a second, shorter time domain when the current exceeds the operational threshold.

10. The device of claim 9 wherein the second time domain is less than ten microseconds in duration.

11. The device of claim 1 wherein the first and second control systems cooperate to enact closed-loop, dynamic voltage-frequency scaling to reduce clock-phase noise due to supply-voltage noise in the device.

12. The device of claim 1 wherein the clock lag is lag of a distributed clock signal in the device relative to a reference clock signal of the device.

13. Enacted in a clocked electronic device, a dynamic voltage-frequency scaling method, comprising:

increasing a supply voltage of the device in response to increasing clock lag in the device;

decreasing the supply voltage when an amount of current drawn through the device exceeds an operational threshold;

increasing clock frequency in the device in response to increasing supply voltage; and

decreasing clock frequency in the device in response to decreasing supply voltage.

14. The method of claim 13 wherein decreasing the supply voltage includes decreasing to a point at which instantaneous power dissipation in the device is below an electronic design power threshold.

15. The method of claim 13 wherein the supply voltage is increased in response to increasing clock lag over a first time domain, but decreased over a second, shorter time domain when the current exceeds the operational threshold.

16. The method of claim 13 wherein the supply voltage is decreased less than one clock cycle after the current exceeds the operational threshold.

17. Enacted in a clocked electronic device, a dynamic voltage-frequency scaling method, comprising:

dividing an electronic design power threshold for the device by a sensed amount of current drawn through the device to compute a load-line voltage;

if the load-line voltage is less than a target supply voltage for the device, setting the supply voltage of the device equal to the load-line voltage;

increasing the clock frequency of the device in response to increasing supply voltage; and

decreasing the clock frequency of the device in response to decreasing supply voltage.

18. The method of claim 17 further comprising setting the supply voltage equal to the target voltage if the target voltage is less than the load-line voltage.

19. The method of claim 17 further comprising sensing the current drawn through the device.

20. The method of claim 17 further comprising nulling the supply voltage to the device if the current exceeds an over-current protection rating for the device.