SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150155373A1
• Filed: 01/30/2015
• Published: 06/04/2015
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SAKATA, Junichiro, OHARA, Hiroki
• Granted Patent: US 9,240,467 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Claims

1. (canceled)

2. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;

forming a source electrode and a drain electrode over and in contact with the oxide semiconductor layer, wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and

removing an upper surface region and side surface regions of the oxide semiconductor layer at the uncovered part of the oxide semiconductor layer,

wherein the crystal region has a c-axis orientation.

3. The method according to claim 2, further comprising the steps of:

adding oxygen into the oxide semiconductor layer; and

performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

4. The method according to claim 2, further comprising the step of heating the oxide semiconductor layer, wherein a concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹/cm³ after heating the oxide semiconductor layer.

5. The method according to claim 2, wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

6. The method according to claim 2, wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;

forming a conductive film over and in contact with the oxide semiconductor layer;

forming a source electrode and a drain electrode by selectively etching the conductive film, wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and

removing an upper surface region and side surface regions at the uncovered part of the oxide semiconductor layer,

wherein the crystal region has a c-axis orientation.

8. The method according to claim 7, wherein the conductive film is selectively etched by wet etching.

9. The method according to claim 7, further comprising the steps of:

adding oxygen into the oxide semiconductor layer; and

performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

10. The method according to claim 7, further comprising the step of heating the oxide semiconductor layer, wherein a concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹/cm³ after heating the oxide semiconductor layer.

11. The method according to claim 7, wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

12. The method according to claim 7, wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;

forming a source electrode and a drain electrode over and in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer extends beyond side edges of the source electrode and side edges of the drain electrode in a channel width direction, and wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; and

removing an upper surface region and side surface regions of the oxide semiconductor layer at the uncovered part of the oxide semiconductor layer,

wherein the crystal region has a c-axis orientation.

14. The method according to claim 13, further comprising the steps of:

adding oxygen into the oxide semiconductor layer; and

performing a second heat treatment on the oxide semiconductor layer after adding oxygen.

15. The method according to claim 13, further comprising the step of heating the oxide semiconductor layer, wherein a concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹/cm³ after heating the oxide semiconductor layer.

16. The method according to claim 13, wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.

17. The method according to claim 13, wherein the oxide semiconductor layer is formed over a gate electrode with a gate insulating film therebetween.