MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER SAVINGS AND BANDWIDTH CONSERVATION IN A RETRY BASED PIPELINE
First Claim
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1. An apparatus comprising:
- a first queue to store a first plurality of entries; and
a second queue to store a second plurality of entries;
wherein each of the first plurality of entries and second plurality of entries is to comprise a first bit to indicate whether an entry is asleep and wherein an arbitration of the entry is to be performed based on a status of the first bit.
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Abstract
Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.
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20 Claims
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1. An apparatus comprising:
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a first queue to store a first plurality of entries; and a second queue to store a second plurality of entries; wherein each of the first plurality of entries and second plurality of entries is to comprise a first bit to indicate whether an entry is asleep and wherein an arbitration of the entry is to be performed based on a status of the first bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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storing a first plurality of entries in a first queue; storing a second plurality of entries in a second queue, wherein each of the first plurality of entries and second plurality of entries is to comprise a first bit to indicate whether an entry is asleep; and determining whether to arbitrate the entry in a retry based pipeline based on a status of the first bit. - View Dependent Claims (14, 15, 16)
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17. A system comprising:
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one or more of a first queue and second queue, wherein the first queue is to store a first plurality of entries and the second queue is to store a second plurality of entries; and a processor to modify a first bit, corresponding to each of the first plurality of entries and second plurality of entries, to indicate whether an entry is asleep, wherein an arbitration of the entry is to be performed based on a status of the first bit. - View Dependent Claims (18, 19, 20)
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Specification