FINFET CROSSPOINT FLASH MEMORY

• US 20150162339A1
• Filed: 12/11/2013
• Published: 06/11/2015
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Divakaruni, Ramachandra, Kumar, Arvind, Radens, Carl J.
• Granted Patent: US 9,305,930 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 with at least two independent gates
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 : characterised by the memory core region

Abstract

A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Claims

1. A semiconductor structure comprising:

a pair of semiconductor fins located on a substrate;

a tunneling gate dielectric located on sidewalls of said pair of semiconductor fins;

a floating gate electrode located between said pair of semiconductor fins and contacting said tunneling gate dielectric;

a control gate dielectric contacting sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode; and

a control gate electrode overlying said control gate dielectric.

2. The semiconductor structure of claim 1, further comprising:

a back gate dielectric located in said substrate and contacting said pair of semiconductor fins; and

a back gate electrode located in said substrate and underlying said back gate dielectric.

3. The semiconductor structure of claim 2, wherein said tunneling gate dielectric is in contact with a bottom surface of said floating gate electrode.

4. The semiconductor structure of claim 2, wherein said back gate dielectric is in physical contact with sidewalls of said tunneling gate dielectric.

5. The semiconductor structure of claim 2, further comprising a shallow trench isolation structure comprising a dielectric material and embedded in said substrate and laterally extending along a lengthwise direction of said pair of semiconductor fins.

6. The semiconductor structure of claim 5, wherein a sidewall of said back gate dielectric and a sidewall of said back gate electrode contact a sidewall of said shallow trench isolation structure.

7. The semiconductor structure of claim 2, further comprising at least another pair of semiconductor fins located on said substrate, wherein a vertical stack including said back gate dielectric and said back gate electrode contiguously extends underneath each of said at least another pair of semiconductor fins.

8. The semiconductor structure of claim 2, wherein an entirety of said pair of semiconductor fins and an entirety of said floating gate electrode are located within an area defined by a periphery of said back gate electrode.

9. The semiconductor structure of claim 2, further comprising:

another pair of semiconductor fins located on said substrate and laterally spaced from said pair of semiconductor fins; and

another back gate dielectric located in said substrate and contacting said another pair of semiconductor fins, wherein each of said pair of semiconductor fins and said another pair of semiconductor fins include a body region, a source region, and a drain region, and all source regions of said pair of semiconductor fins and said another pair of semiconductor fins are electrically shorted, and all drain regions of said pair of semiconductor fins and said another pair of semiconductor fins are electrically shorted.

10. The semiconductor structure of claim 1, wherein sidewalls of said floating gate dielectric that do not contact said pair of semiconductor fins are vertically coincident with sidewalls of said control gate dielectric.

11. The semiconductor structure of claim 1, wherein each of said pair of semiconductor fins comprises:

a body region underlying said control gate electrode;

a source region including a portion that does not underlie said control gate electrode; and

a drain region including a portion that does not underlie said control gate electrode and laterally spaced from said source region by said body region.

12. A method of forming a semiconductor structure comprising:

forming a pair of semiconductor fins on a substrate;

forming a tunneling gate dielectric on proximal sidewalls of said pair of semiconductor fins;

forming a floating gate electrode between said pair of semiconductor fins on sidewalls of said tunneling gate dielectric;

forming a control gate dielectric on distal sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode; and

forming a control gate electrode over said control gate dielectric.

13. The method of claim 12, further comprising forming a vertical stack including a back gate dielectric and a back gate electrode in said substrate and underneath said pair of semiconductor fins.

14. The method of claim 13, further comprising forming a shallow trench isolation structure in said substrate, wherein sidewalls of said back gate electrode and said back gate dielectric contact sidewalls of said shallow trench isolation structure.

15. The method of claim 14, further comprising:

forming a dielectric spacer laterally surrounding said pair of semiconductor fins and filling a space between said pair of semiconductor fins;

forming a trench in said substrate employing said dielectric spacer as an etch mask; and

forming said shallow trench isolation structure by filling said trench with a dielectric material.

16. The method of claim 14, further comprising:

forming another semiconductor fin on said substrate;

removing said another semiconductor fin by an etch process, while said pair of semiconductor fins are protected from said etch process by a patterned mask layer, wherein a line cavity is formed in a volume from which said another semiconductor fins is removed;

etching a portions of said substrate underlying said line cavity; and

forming said shallow trench isolation structure by filling said trench with a dielectric material.

17. The method of claim 14, further comprising forming at least another pair of semiconductor fins on said substrate, wherein a vertical stack including said back gate dielectric and said back gate electrode contiguously extend underneath each of said at least another pair of semiconductor fins.

18. The method of claim 14, further comprising:

forming another pair of semiconductor fins on said substrate;

forming another back gate electrode underneath said another pair of semiconductor fins, wherein said shallow trench isolation structure electrically isolates said another back gate electrode from said back gate electrode;

forming a body region, a source region, and a drain region in each of said pair of semiconductor fins and said another pair of semiconductor fins; and

electrically shorting all source regions of said pair of semiconductor fins and said another pair of semiconductor fins, and electrically shorting all drain regions of said pair of semiconductor fins and said another pair of semiconductor fins.

19. The method of claim 12, further comprising:

depositing a floating gate material layer on said tunneling gate dielectric; and

isotropically etching said floating gate material layer, wherein a remaining portion of said floating gate material layer is present between said pair of semiconductor fins to form said floating gate electrode.

20. The method of claim 19, further comprising:

forming a disposable gate structure straddling said pair of semiconductor fins;

forming a source region and a drain region in each of said pair of semiconductor fins; and

removing said disposable gate structure prior to forming said tunneling gate dielectric.