METHODS AND APPARATUS FOR SIGNALING ON A DIFFERENTIAL LINK

• US 20150163075A1
• Filed: 12/08/2014
• Published: 06/11/2015
• Est. Priority Date: 03/14/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenborn, Zale T.
• Granted Patent: US 9,503,289 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Claims

1-12. -12. (canceled)

13. A processor device comprising:

an interface to couple the processor device to another device, wherein the interface comprises interface logic, implemented at least in part in hardware, to;

enter a low power state;

send a differential signal to the other device over a differential, point-to-point serial data link for at least a predetermined length of time to initiate a transition from the low power state to a data transmitting state; and

transmit data to the other device within the data transmitting state.

14. The processor device of claim 13, wherein the differential signal comprises an in-band signal.

15. The processor device of claim 13, wherein transmission of the data comprises a high speed data transmission.

16. The processor device of claim 15, wherein the data is to be transmitted at at least 2.5 Gbit per second.

17. The processor device of claim 13, wherein the interface logic comprises transmitter logic.

18. The processor device of claim 17, wherein the interface logic further comprises receiver logic.

19. The processor device of claim 13, wherein the low power state comprises a non-zero power state.

20. The processor device of claim 19, wherein power is to be applied to the processor device during the low power state.

21. The processor device of claim 13, wherein the differential signal is to comprise a constant voltage signal over the duration of time.

22. The processor device of claim 21, wherein the differential signal is to comprise a direct current (DC) signal of a threshold voltage.

23. The processor device of claim 13, wherein the link is to support a serial data link protocol.

24. The processor device of claim 23, wherein the link protocol comprises a general purpose input/output interconnect protocol.

25. The processor device of claim 13, wherein the duration of time is based on a clock of the processor.

26. The processor device of claim 13, further comprising a queue to queue data for transmission in the data transmitting state.

27. A processor device comprising:

an interface to couple to another device, wherein the interface comprises logic, implemented at least in part in hardware, to;

enter a reduced power state;

receive a differential signal transmitted over a differential, point-to-point serial data link for at least a predetermined duration of time during a low power state;

interpret the signal as a signal is to initiate a transition from the low power state to a data transmitting state; and

transition from the reduced power state to a normal power state based at least in part on the wake signal.

28. An apparatus comprising:

an interface to couple the processor device to another device, wherein the interface comprises interface logic, to comprise transmitter logic and receiver logic, the interface logic is implemented at least in part in hardware and comprises at least one transistor, at least one resistor, and at least one capacitor, and the transmitter logic is to;

send a differential signal to the other device over a differential, point-to-point serial data link during a low power state for at least a predetermined duration of time, wherein the signal is to comprise a steady voltage signal during the duration and is to initiate a transition from the low power state to a data transmitting state;

transition from the low power state to a data transmitting state; and

transmit high speed data to the other device within the data transmitting state, wherein the low power state is to comprise a non-zero power state.

29. A system comprising:

a data link comprising a differential, point-to-point serial data link;

a particular device;

a processor communicatively coupled to the particular device using the data link, the processor comprising interface logic to;

enter a low power state;

send a differential signal to the particular device over a differential, point-to-point serial data link for at least a predetermined duration of time, wherein the signal is to initiate a transition from the low power state to a data transmitting state; and

transmit data to the particular device within the data transmitting state.

30. The system of claim 29, wherein the interface logic is further to transition from a low power state to a reset state.

31. The system of claim 29, wherein the particular device is to comprise receiver logic to:

receive the differential signal; and

interpret the differential signal as a wake signal.

32. The system of claim 29, wherein the particular device comprises a peripheral device.