METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL POLISH AND CLEAN

• US 20150179432A1
• Filed: 12/19/2013
• Published: 06/25/2015
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Suen, Shich-Chang, Liu, Chi-Jen, Wu, Li-Chieh, Chen, Liang-Guang, Yen, Ming-Liang, Chuang, Ying-Liang
• Granted Patent: US 9,449,841 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B24B 37/20 Lapping pads for working plane surfaces
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/67051 using mainly spraying means, e.g. nozzles
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions, the MG layer being formed on the ILD regions;

performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and

cleaning the planarized MG layer using a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW).

2. The method of claim 1, further comprising:

forming a metal oxide layer on the MG layer simultaneously with cleaning the planarized MG layer.

3. The method of claim 1, wherein the cleaning the planarized MG layer using the O₃/DIW solution comprises removing organic residue from CMP slurry by a reaction:

CH₂+3O₃→

CO₂+3O₂+3H₂O

the organic residue including a functional group —

CH₂.

4. The method of claim 1, wherein the O₃/DIW solution is generated by an O₃/DIW generator coupled to a polishing unit of the CMP system, and wherein the cleaning the planarized MG layer includes buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in the polishing unit, the polishing unit including a pipeline coupled to the O₃/DIW generator to supply the O₃/DIW solution to the buffing pad.

5. The method of claim 1, wherein an O₃/DIW generator is coupled to a cleaning unit of the CMP system to supply the O₃/DIW solution.

6. The method of claim 5, wherein the cleaning unit includes a water tank coupled to the O₃/DIW generator, and wherein the cleaning the planarized MG layer includes cleaning a surface of the semiconductor structure in the water tank further coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution contained in the water tank.

7. The method of claim 5, wherein the cleaning unit includes a spray nozzle coupled to the O₃/DIW generator, and wherein the cleaning the planarized MG layer includes cleaning the a surface of the semiconductor structure using the spray nozzle further coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution to form an O₃/DIW fog to be sprayed from the spray nozzle to the surface of the semiconductor structure.

8. The method of claim 5, wherein the cleaning unit includes:

a brush configured to scrub a surface of the semiconductor structure; and

a spray nozzle coupled to the O₃/DIW generator,

wherein the cleaning the planarized MG layer includes scrubbing the surface of the semiconductor structure using the brush and the O₃/DIW solution sprayed from the spray nozzle.

9. The method of claim 1, wherein the cleaning the planarized MG layer includes:

buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in a polishing unit, the polishing unit including a pipeline coupled to an O₃/DIW generator configured to supply the O₃/DIW solution to the buffing pad; and

cleaning the surface of the semiconductor structure in a water tank coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution contained in the water tank, the water tank coupled to the O₃/DIW generator configured to supply the O₃/DIW solution to the water tank.

10. The method of claim 1, wherein the cleaning the planarized MG layer includes:

buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in a polishing unit, the polishing unit including a pipeline coupled to an O₃/DIW generator configured to supply the O₃/DIW solution to the buffing pad; and

cleaning the surface of the semiconductor structure using a spray nozzle coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution to form an O₃/DIW fog to be sprayed from the spray nozzle to the surface of the semiconductor structure, the spray nozzle coupled to the O₃/DIW generator.

11. The method of claim 1, wherein the cleaning the planarized MG layer includes:

buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in a polishing unit, the polishing unit including a pipeline coupled to an O₃/DIW generator configured to supply the O₃/DIW solution to the buffing pad; and

scrubbing the surface of the semiconductor structure using a brush and the O₃/DIW solution sprayed from a spray nozzle, the spray nozzle coupled to the O₃/DIW generator.

12. The method of claim 1, wherein a pH value of the O₃/DIW solution is in a range from about 4 to about 9.

13. The method of claim 1, wherein a concentration of the O₃ dissolved in the O₃/DIW solution is in a range from about 5 ppm to about 70 ppm.

14. The method of claim 1, further comprising:

drying the cleaned semiconductor structure;

depositing an etch stop layer (ESL) over the ILD regions and the MG layer; and

forming a contact hole through the ESL and the ILD regions.

15. A chemical mechanical polishing (CMP) system, the CMP system comprising:

a O₃/DIW generator configured to generate a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW);

a polishing unit including components for planarizing and buffing a surface of a semiconductor structure, the polishing unit including a pipeline coupled to the O₃/DIW generator to provide the O₃/DIW solution for buffing; and

a cleaning unit coupled to the O₃/DIW generator and configured to clean the planarized surface of the semiconductor structure using the O₃/DIW solution.

16. The CMP system of claim 15, wherein the cleaning unit includes a spray nozzle coupled to the O₃/DIW generator and configured to supply the O₃/DIW solution to the semiconductor structure.

17. The CMP system of claim 16, wherein the cleaning unit includes a brush configured to scrub the surface of the semiconductor structure when the spray nozzle sprays the O₃/DIW solution to the semiconductor structure.

18. The CMP system of claim 16, wherein the spray nozzle is coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution supplied by the O₃/DIW generator to form an O₃/DIW fog to be sprayed from the spray nozzle to the semiconductor structure.

19. The CMP system of claim 15, wherein the cleaning unit includes a water tank coupled to a megasonic generator and the O₃/DIW generator, the megasonic generator being configured to provide an oscillation to the O₃/DIW solution contained in the water tank.

20. A semiconductor device, comprising:

a plurality of interlayer dielectric (ILD) regions;

a metal gate (MG) layer configured to fill a trench between two adjacent ILD regions;

an oxide layer formed on the MG layer; and

an etch stop layer (ESL) deposited on the oxide layer,

wherein the MG layer and the ILD regions have a coplanar top surface,

wherein the coplanar top surface is cleaned using a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW), and

wherein the oxide layer is formed by oxidizing a metal in the MG layer using the O₃/DIW solution.