DYNAMIC ERROR VECTOR MAGNITUDE COMPENSATION

• US 20150180518A1
• Filed: 12/18/2014
• Published: 06/25/2015
• Est. Priority Date: 12/23/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Whittaker, Edward John Wemyss
• Granted Patent: US 9,660,600 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/421 Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit
• CPC Class Codes: H03F 2200/423 Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/40 Circuits

Abstract

Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

Claims

1. An electronically-implemented method comprising:

selectively charging a capacitor based at least partly on an amount of time that a power amplifier is disabled between successive transmission bursts;

generating a bias signal based at least partly on an amount of charge stored on the capacitor; and

biasing the power amplifier with the bias signal such that the power amplifier has a substantially constant gain.

2. The method of claim 1 further comprising fully charging, prior to said selectively charging, the capacitor to a full amount of charge prior to the power amplifier being turned on after a cold start.

3. The method of claim 1 wherein said selectively charging includes charging the capacitor to less than a full amount of charge.

4. The method of claim 1 further comprising scaling a reference signal generated from the capacitor, said generating the bias signal being based at least partly on the scaled reference signal.

5. The method of claim 4 wherein a digital-to-analog converter performs said scaling.

6. The method of claim 1 wherein said selectively charging is further based at least partly on a voltage level of the power supply voltage.

7. A power amplifier system comprising:

a power amplifier configured to receive a bias signal, receive a radio frequency (RF) signal, and generate an amplified RF signal;

a compensation circuit including a capacitor configured to charge and discharge, the compensation circuit configured to charge the capacitor based at least partly on an amount of time that the power amplifier is turned off between successive transmission bursts of the power amplifier, and the compensation circuit configured to generate a compensation signal based at least partly on an amount of charge stored on the capacitor; and

bias circuit configured to generate the bias signal based at least partly on the compensation signal.

8. The power amplifier system of claim 7 wherein the compensation circuit is configured to charge the capacitor based at least partly on an enable signal of the power amplifier.

9. The power amplifier system of claim 8 wherein the bias circuit is configured to receive the enable signal and to selectively pulse an output of the power amplifier based at least partly on the enable signal.

10. The power amplifier system of claim 7 wherein the bias circuit is configured to control the bias signal such that a gain of the power amplifier is substantially constant as the amount of time between successive transmission bursts of the power amplifier changes.

11. The power amplifier system of claim 7 wherein the power amplifier, the compensation circuit, and the bias circuit are included within a single package.

12. The power amplifier system of claim 7 wherein the power amplifier includes a bipolar power amplifier transistor having a base and a collector, the base configured to receive the bias signal, and the collector configured to provide the amplified RF signal.

13. The power amplifier system of claim 7 wherein the compensation circuit includes a power supply boost circuit configured to adjust current to charge the capacitor based at least partly on a voltage level of a power supply voltage.

14. The power amplifier system of claim 7 wherein the compensation circuit includes a scaling circuit configured to generate the compensation signal based at least partly on scaling a signal from the capacitor, and the bias circuit is configured to generate the bias signal based at least partly on a combination of the compensation signal and a reference signal.

15. An apparatus comprising:

an amplifier configured to amplify an input signal;

a compensation circuit configured to generate a compensation signal based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts of the amplifier; and

a bias circuit configured to receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

16. The apparatus of claim 15 wherein the compensation circuit includes a digital-to-analog converter configured to receive a reference voltage from the capacitor and to generate the compensation signal based at least partly on the reference voltage and a digital-to-analog converter control word.

17. The apparatus of claim 15 wherein the compensation circuit includes a capacitor configured to charge and discharge, the compensation circuit configured to charge the capacitor based at least partly on the amount of time that the amplifier is turned off between successive transmission bursts of the amplifier.

18. The apparatus of claim 17 wherein the compensation circuit is configured to charge the capacitor to a full amount of charge responsive to the amplifier being turned on after a cold start.

19. The apparatus of claim 15 wherein the amplifier includes a power amplifier.

20. The apparatus of claim 19 configured as a mobile device, the mobile device including the power amplifier, the compensation circuit, the bias circuit, and an antenna configured to transmit an RF signal from the power amplifier.