DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

• US 20150186261A1
• Filed: 11/06/2014
• Published: 07/02/2015
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: LIN, Chien-Cheng, LIANG, Chia-Chi, HUANG, Chang-Chieh, LEE, Jie-Hao
• Granted Patent: US 9,632,880 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

Claims

1. A data storage device, comprising:

a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,

wherein;

the microcontroller is configured to allocate the flash memory to provide a first run-time write block from the blocks;

between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table;

the logical-to-physical address mapping table is provided within the flash memory; and

the first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller establishes the first physical-to-logical address mapping table in accordance with write operations issued from the host to write the first run-time write block.

3. The data storage device as claimed in claim 2, wherein:

after writing user data of a predetermined size into the first run-time write block, the microcontroller is configured to update the logical-to-physical address mapping table in accordance with a section of the first physical-to-logical address mapping table corresponding to the user data of the predetermined size; and

the predetermined size is smaller than a total size of the first run-time write block.

4. The data storage device as claimed in claim 2, wherein:

after writing a series of user data, each shorter than one page, into the first run-time write block, the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table at intervals between subsequent write operations of the first run-time write block.

5. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to allocate the flash memory to provide the first run-time write block when a first table-outdated block between the blocks of the flash memory and corresponding to the first physical-to-logical address mapping table is full; and

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the first physical-to-logical address mapping table at intervals between write operations of the first run-time write block.

6. The data storage device as claimed in claim 5, wherein:

the microcontroller is configured to further allocate the flash memory to provide a second run-time write block from the blocks when a second table-outdated block between the blocks of the flash memory and corresponding to a second physical-to-logical address mapping table established in the random access memory is full;

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the second physical-to-logical address mapping table at intervals between write operations of the second run-time write block;

the first run-time write block and the first table-outdated block are provided for write operations of a first type; and

the second run-time write block and the second table-outdated block are provided for write operations of a second type.

7. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to allocate the flash memory to provide the first run-time write block in a power recovery process when a write operation on a first table-outdated block between the blocks of the flash memory and corresponding to the first physical-to-logical address mapping table was interrupted by an unexpected power-off event;

the microcontroller is configured to restore the first physical-to-logical address mapping table in the power recovery process; and

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the restored first physical-to-logical address mapping table at intervals between write operations of the first run-time write block.

8. The data storage device as claimed in claim 7, wherein:

the microcontroller is configured to further allocate the flash memory to provide a second run-time write block from the blocks in the power recovery process when a write operation on a second table-outdated block between the blocks of the flash memory and corresponding to a second physical-to-logical address mapping table established in the random access memory was interrupted by the unexpected power-off event;

the microcontroller is configured to restore the second physical-to-logical address mapping table in the power recovery process;

the microcontroller is configured to update the logical-to-physical address mapping table in accordance with the restored second physical-to-logical address mapping table at intervals between write operations of the second run-time write block;

the first run-time write block and the first table-outdated block are provided for write operations of a first type; and

the second run-time write block and the second table-outdated block are provided for write operations of a second type.

9. The data storage device as claimed in claim 1, wherein:

the microcontroller is further configured to use an indicator to indicate a section of the first physical-to-logical address mapping table that has not been used in the update of the logical-to-physical address mapping table yet; and

the microcontroller is configured to search the first physical-to-logical address mapping table in accordance with the indicator.

10. A flash memory control method, comprising:

allocating a flash memory to provide a first run-time write block from a plurality of blocks of the flash memory, each block comprising a plurality of pages; and

between a first write operation and a second write operation of the first run-time write block, updating a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table,

wherein;

the logical-to-physical address mapping table is provided within the flash memory; and

the first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

11. The flash memory control method as claimed in claim 10, wherein:

the first physical-to-logical address mapping table is established in accordance with write operations issued from a host to write the first run-time write block.

12. The flash memory control method as claimed in claim 11, wherein:

after writing user data of a predetermined size into the first run-time write block, the logical-to-physical address mapping table is updated in accordance with a section of the first physical-to-logical address mapping table corresponding to the user data of the predetermined size; and

the predetermined size is smaller than a total size of the first run-time write block.

13. The flash memory control method as claimed in claim 11, wherein:

after a series of user data each shorter than one page is written into the first run-time write block, the logical-to-physical address mapping table is updated in accordance with the first physical-to-logical address mapping table at intervals between subsequent write operations of the first run-time write block.

14. The flash memory control method as claimed in claim 10, wherein:

the flash memory is allocated to provide the first run-time write block when a first table-outdated block between the blocks of the flash memory and corresponding to the first physical-to-logical address mapping table is full; and

the logical-to-physical address mapping table is updated in accordance with the first physical-to-logical address mapping table at intervals between write operations of the first run-time write block.

15. The flash memory control method as claimed in claim 14, further comprising:

allocating the flash memory to provide a second run-time write block from the blocks when a second table-outdated block between the blocks of the flash memory and corresponding to a second physical-to-logical address mapping table established in the random access memory is full;

updating the logical-to-physical address mapping table in accordance with the second physical-to-logical address mapping table at intervals between write operations of the second run-time write block,

wherein;

the first run-time write block and the first table-outdated block are provided for write operations of a first type; and

the second run-time write block and the second table-outdated block are provided for write operations of a second type.

16. The flash memory control method as claimed in claim 10, wherein:

the flash memory is allocated to provide the first run-time write block in a power recovery process when a write operation on a first table-outdated block between the blocks of the flash memory and corresponding to the first physical-to-logical address mapping table was interrupted by an unexpected power-off event;

the first physical-to-logical address mapping table is restored in the power recovery process; and

the logical-to-physical address mapping table is updated in accordance with the restored first physical-to-logical address mapping table at intervals between write operations of the first run-time write block.

17. The flash memory control method as claimed in claim 16, further comprising:

allocating the flash memory to provide a second run-time write block from the blocks in the power recovery process when a write operation on a second table-outdated block between the blocks of the flash memory and corresponding to a second physical-to-logical address mapping table established in the random access memory was interrupted by the unexpected power-off event;

restoring the second physical-to-logical address mapping table in the power recovery process;

updating the logical-to-physical address mapping table in accordance with the restored second physical-to-logical address mapping table at intervals between write operations of the second run-time write block,

wherein;

the first run-time write block and the first table-outdated block are provided for write operations of a first type; and

the second run-time write block and the second table-outdated block are provided for write operations of a second type.

18. The flash memory control method as claimed in claim 10, further comprising:

using an indicator to indicate a section of the first physical-to-logical address mapping table that has not been used in the update of the logical-to-physical address mapping table yet; and

searching the first physical-to-logical address mapping table in accordance with the indicator.