DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

• US 20150186264A1
• Filed: 11/06/2014
• Published: 07/02/2015
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: LIN, Chien-Cheng, LIANG, Chia-Chi, HUANG, Chang-Chieh, LEE, Jie-Hao
• Granted Patent: US 9,542,278 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 : Online error correction
• CPC Class Codes: G11C 2211/5641 : Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage device and a flash memory control method with high efficiency are disclosed. The random access memory of the data storage device is allocated to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table. When recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller of the data storage device is configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.

Claims

1. A data storage device, comprising:

a flash memory, providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,

wherein;

the microcontroller is configured to build a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory;

the microcontroller is further configured to allocate the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table; and

when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.

2. The data storage device as claimed in claim 1, wherein:

when recording a logical address corresponding to an old logical-to-physical address mapping table that has appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured to perform an update of the old logical-to-physical address mapping table within the collection and update area.

3. The data storage device as claimed in claim 2, wherein:

the microcontroller is configured to update a logical-to-physical address mapping relationship recorded in the flash memory in accordance with the logical-to-physical address mapping tables collected and updated in the collection and update area.

4. The data storage device as claimed in claim 2, wherein:

the microcontroller is configured to invalidate the collection and update area when the collection and update area is insufficient for the logical-to-physical address mapping tables corresponding to logical addresses recorded in the physical-to-logical address mapping table.

5. The data storage device as claimed in claim 4, wherein:

the microcontroller is configured to upload the logical-to-physical address mapping tables collected and updated in the collection and update area to the flash memory to update a logical-to-physical address mapping relationship recorded in the flash memory when the collection and update area is not invalid.

6. The data storage device as claimed in claim 5, wherein:

the microcontroller is configured to discard data in the collection and update area when the collection and update area is invalid.

7. The data storage device as claimed in claim 6, wherein:

when the data in the collection and update area has been discarded, the microcontroller is configured to scan the physical-to-logical address mapping table to download logical-to-physical address mapping tables that correspond to the logical addresses recorded in the physical-to-logical address mapping table from the flash memory to the random access memory; and

the logical-to-physical address mapping tables downloaded into the random access memory along with scanning the physical-to-logical address mapping table are updated on the random access memory and then uploaded back to the flash memory.

8. A flash memory control method, comprising:

providing a random access memory for a flash memory, the flash memory providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of pages;

building a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory; and

allocating the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded in the physical-to-logical address mapping table,

wherein when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the new logical-to-physical address mapping table is collected into the collection and update area and an update of the new logical-to-physical address mapping table is performed within the collection and update area.

9. The flash memory control method as claimed in claim 8, wherein:

when recording a logical address corresponding to an old logical-to-physical address mapping table that has appeared in the collection and update area into the physical-to-logical address mapping table, an update of the old logical-to-physical address mapping table is performed within the collection and update area.

10. The flash memory control method as claimed in claim 9, further comprising:

updating a logical-to-physical address mapping relationship recorded in the flash memory in accordance with the logical-to-physical address mapping tables collected and updated in the collection and update area.

11. The flash memory control method as claimed in claim 9, further comprising:

invalidating the collection and update area when the collection and update area is insufficient for the logical-to-physical address mapping tables corresponding to logical addresses recorded in the physical-to-logical address mapping table.

12. The flash memory control method as claimed in claim 11, further comprising:

uploading the logical-to-physical address mapping tables collected and updated in the collection and update area to the flash memory to update a logical-to-physical address mapping relationship recorded in the flash memory when the collection and update area is not invalid.

13. The flash memory control method as claimed in claim 12, further comprising:

discarding data in the collection and update area when the collection and update area is invalid.

14. The flash memory control method as claimed in claim 13, wherein:

when the data in the collection and update area has been discarded, the physical-to-logical address mapping table is scanned to download logical-to-recorded in the physical-to-logical address mapping table from the flash memory to the random access memory; and

the logical-to-physical address mapping tables downloaded into the random access memory along with scanning the physical-to-logical address mapping table are updated on the random access memory and then uploaded back to the flash memory.