LOCAL THINNING OF SEMICONDUCTOR FINS

• US 20150200276A1
• Filed: 01/16/2014
• Published: 07/16/2015
• Est. Priority Date: 01/16/2014
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Divakaruni, Ramachandra, Radens, Carl J.
• Granted Patent: US 9,431,523 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Claims

1. A method of forming a semiconductor structure comprising:

forming a semiconductor fin on a substrate;

forming a planarization dielectric layer over said semiconductor fin;

physically exposing a portion of a top surface of said semiconductor fin while another portion of said top surface of said semiconductor fin is covered with said planarization dielectric layer;

converting a surface portion of said semiconductor fin into a semiconductor oxide portion employing an oxygen cluster implantation process in which clusters of oxygen atoms are implanted into said surface portion of said semiconductor fin; and

removing said semiconductor oxide portion.

2. The method of claim 1, further comprising

forming a disposable gate structure across said semiconductor fin, wherein said planarization dielectric layer is formed around said disposable gate structure and over said semiconductor fin;

and

forming a gate cavity by removing said disposable gate structure selective to said planarization dielectric layer, wherein said physically exposed portion of said top surface of said semiconductor fin is formed underneath said gate cavity.

3. The method of claim 2, further comprising:

forming another semiconductor fin on said substrate; and

masking said another semiconductor fin with a combination of a patterned masking layer and said planarization dielectric layer during said oxygen cluster implantation process.

4. The method of claim 3, wherein said disposable gate structure is formed across said another semiconductor fin, and said patterned masking layer does not cover a region of said gate cavity that overlies said semiconductor fin and covers another region of said gate cavity that overlies said another semiconductor fin.

5. The method of claim 2, further comprising forming a gate spacer around said disposable gate stack prior to formation of said planarization dielectric layer, wherein said gate spacer blocks said clusters of oxygen atoms during said oxygen cluster implantation process.

6. The method of claim 1, further comprising forming a stack of a gate dielectric and a gate electrode directly on a surface of said semiconductor fin from which said semiconductor oxide portion is removed.

7. A method of forming a semiconductor structure comprising:

forming a plurality of semiconductor fins including two outermost semiconductor fins on a substrate;

forming semiconductor oxide portions on outermost sidewalls of said plurality of semiconductor fins employing an oxygen cluster implantation process in which clusters of oxygen atoms are implanted into physically exposed and unshaded surface portions of said two outermost semiconductor fins while inner sidewalls of said two outermost semiconductor fins are at least partially shaded; and

laterally thinning said two outermost semiconductor fins by removing said semiconductor oxide portions.

8. The method of claim 7, wherein said plurality of semiconductor fins further includes at least one nested semiconductor fin located between said two outermost semiconductor fins, wherein sidewalls of said at least one nested semiconductor fin are at least partially shaded during said oxygen cluster implantation process.

9. The method of claim 7, wherein additional semiconductor oxide portions are formed on inner sidewalls of said two outermost semiconductor fins, wherein said semiconductor oxide portions on said outermost sidewalls of said plurality of semiconductor fins have a greater thickness than said additional semiconductor oxide portions.

10. The method of claim 7, wherein said plurality of semiconductor fins is formed within a plurality of fin stacks, wherein each of said fin stacks includes a semiconductor fin and a fin cap structure, and said fin cap structures provide shading of said clusters of oxygen atoms during said oxygen cluster implantation process.

11. The method of claim 10, wherein said fin cap structures provide full shading of inner sidewalls of said two outermost semiconductor fins, and no semiconductor oxide portion is formed on said inner sidewalls of said two outermost semiconductor fins by said oxygen cluster implantation process.

12. The method of claim 10, further comprising removing said fin cap structures after said oxygen cluster implantation process.

13. The method of claim 8, further comprising forming a gate stack across said plurality of semiconductor fins after said two outermost semiconductor fins are thinned.

14. A semiconductor structure comprising:

a semiconductor fin located on a substrate, said semiconductor fin having a same semiconductor composition throughout and including a body region, a fin source region, and a fin drain region, wherein a top surface of said body region is recessed relative to top surfaces of said fin source region and said fin drain region; and

a gate stack straddling said body region, wherein sidewalls of a gate dielectric within said gate stack contact sidewalls of said fin source region and said fin drain region.

15. The semiconductor structure of claim 14, further comprising another semiconductor fin located on said substrate, wherein a top surface of another body region that is present within said another semiconductor fin is coplanar with top surfaces of another fin source region and another fin drain region that are present within said another semiconductor fin.

16. The semiconductor structure of claim 15, wherein said top surface of said another body region is within a same horizontal plane as said top surfaces of said fin source region and said fin drain region of said semiconductor fin.

17. The semiconductor structure of claim 14, wherein gate stack straddles said another semiconductor fin.

18. The semiconductor structure of claim 14, further comprising a gate spacer including inner sidewalls that vertically coincide with said sidewalls of said gate dielectric.

19. The semiconductor structure of claim 14, wherein said fin source region and said fin drain region have a greater width than an upper portion of said body region.

20. A semiconductor structure comprising a semiconductor fin located on a substrate and including a first sidewall and a second sidewall, wherein said first and second sidewalls extend along a lengthwise direction of said semiconductor fin, a planar upper portion of said first sidewall is contained within a first planar vertical plane, a planar upper portion of said second sidewall is contained within a second planar vertical plane that is parallel to said first planar vertical plane, and a portion of said first sidewall includes a curved surface that protrudes outward from said first vertical plane by a distance that is greater than a maximum of any lateral deviation of said second sidewall from said second planar vertical plane.

21. The semiconductor structure of claim 20, further comprising another semiconductor fin located on said substrate and including a pair of sidewalls that extend along a lengthwise direction of said another semiconductor fin, wherein said pair of sidewalls include planar portions having a uniform width, and a maximum lateral deviation of each of said pair of sidewalls is the same as said maximum of any lateral deviations of said second sidewall.

22. The semiconductor structure of claim 20, wherein said curved surface is a concave surface having a same curvature along said lengthwise direction of said semiconductor fin.

23. The semiconductor structure of claim 22, wherein said second sidewall includes another concave surface having a lesser radius of curvature than said concave surface.

24. The semiconductor structure of claim 20, wherein said substrate is a bulk semiconductor substrate, said first and second sidewalls are contiguously adjoined to said bulk semiconductor substrate, and a bottommost portion of said first sidewall is vertically coincident with a most distal portion of said curved surface.

25. The semiconductor structure of claim 20, further comprising a gate stack straddling said semiconductor fin.