DESIGN AUTOMATION FOR MONOLITHIC 3D DEVICES

• US 20150205903A1
• Filed: 03/29/2015
• Published: 07/23/2015
• Est. Priority Date: 04/15/2013
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Granted Patent: US 10,127,344 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

Claims

1. A method of designing a 3D Integrated Circuit, the method comprising:

performing partitioning to at least a first strata and a second strata;

then

performing a first placement of said first strata using a 2D placer executed by a computer,

wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,

wherein said partitioning comprises a partition between logic and memory, and

wherein said logic comprises at least one decoder representation for said memory.

2. The method according to claim 1, further comprising:

performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

3. The method according to claim 1,

wherein said performing placement comprises placement of said at least one decoder representation for at least a portion of said memory, and

wherein the placement of said at least a portion of said memory is defined by the placement of said at least one decoder representation.

4. The method according to claim 1,

wherein said memory comprises at least a first memory and a second memory,

wherein said first memory comprises first memory decoder representations and said second memory comprises second memory decoder representations, and

wherein said 2D placer is set so said second memory decoder representations are not placed within a rectangle defined by the placement of said first memory decoder representations.

5. The method according to claim 1,

wherein said decoder representation is placed on said first strata, and

wherein an actual memory decoder and associated bit cells are placed on said second strata, and

wherein placement of said actual memory decoder and associated bit cells is based on said decoder representation placement.

6. The method according to claim 1,

wherein said at least one decoder representation has a virtual size with width of contacts for said through silicon vias, and

wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder.

7. A method of designing a 3D Integrated Circuit, the method comprising:

performing partitioning to at least a first strata and a second strata;

then

performing a first placement of said first strata using a 2D placer executed by a computer,

wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,

wherein said partitioning comprises a partition between logic and memory, and

wherein said logic comprises at least one decoder for said memory.

8. The method according to claim 7,

wherein said second strata comprises mostly memory bit cells.

9. The method according to claim 7,

wherein said memory comprises at least a first memory and a second memory,

wherein said first memory comprises first memory decoders and said second memory comprises second memory decoders, and

wherein said 2D placer is set so said second memory decoders are not placed within a rectangle defined by the placement of said first memory decoders.

10. The method according to claim 7,

wherein performing a second placement comprises the use of said 2D placer.

11. The method according to claim 7,

wherein said at least one decoder has a virtual size with width of contacts for said through silicon vias, and

wherein said performing a first placement comprises using a decoder representation of said decoder.

12. The method according to claim 7, further comprising:

performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

13. The method according to claim 7, further comprising:

performing a synthesis step using two libraries.

14. A method of designing a 3D Integrated Circuit, the method comprising:

performing partitioning to at least a first strata and a second strata;

then

performing a first placement of said first strata using a 2D placer executed by a computer,

wherein said 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,

wherein said partitioning comprises splitting a plurality of cells into a high performance group to said first strata and a low performance group to said second strata.

15. The method according to claim 14,

wherein said performing a second placement comprises the use of said 2D placer.

16. The method according to claim 14,

wherein said first strata utilizes a first process design rule set,

wherein said second strata utilizes a second process design rule set, and

wherein said first process design rule set is at least one process node more advanced than said second process design rule set.

17. The method according to claim 14, further comprising:

performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

18. The method according to claim 14, further comprising:

performing a synthesis step using two libraries.

19. The method according to claim 14,

wherein said splitting comprises steps of selecting cells that add minimum connections between said first strata and said second strata.

20. The method according to claim 14,

wherein said low performance group comprises low power cells.