LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME

• US 20150207039A1
• Filed: 01/27/2015
• Published: 07/23/2015
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: LEE, Sum Geun, JIN, Sang Ki, SHIN, Jin Cheol, KIM, Jong Kyu, LEE, So Ra, LEE, Chung Hoon
• Granted Patent: US 9,343,631 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 33/0008 having p-n or hi-lo junctions
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, including a substrate, a light-emitting structure disposed on a first surface of the substrate, the light-emitting structure including an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range, and first and second distributed Bragg reflectors (DBRs) disposed on a second surface of the substrate. The first DBR is disposed closer to the substrate than the second DBR, the first wavelength range comprises a blue wavelength range, the first DBR comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range, and the second DBR comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range.

Claims

1. A light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, comprising:

a substrate;

a light-emitting structure disposed on a first surface of the substrate, the light-emitting structure comprising an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range; and

first and second distributed Bragg reflectors (DBRs) disposed on a second surface of the substrate,

wherein;

the first DBR is disposed closer to the substrate than the second DBR;

the first wavelength range comprises a blue wavelength range;

the first DBR comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range; and

the second DBR comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range.

2. The light-emitting diode chip of claim 1, further comprising a phosphor disposed on the light-emitting structure,

wherein the phosphor is configured to convert light of the second wavelength range.

3. The light-emitting diode chip of claim 2, wherein the second wavelength range comprises a red wavelength range.

4. The light-emitting diode chip of claim 2, wherein the second wavelength range comprises a green wavelength range.

5. The light-emitting diode chip of claim 1, wherein the first DBR contacts the second surface of the substrate.

6. The light-emitting diode chip of claim 1, wherein a surface roughness of the second surface of the substrate is 3 μ

m or less.

7. The light-emitting diode chip of claim 1, wherein the first surface of the substrate comprises a patterned surface.

8. The light-emitting diode chip of claim 1, wherein the area of the substrate is at least 90,000 μ

m².

9. The light-emitting diode chip of claim 8, further comprising light-emitting cells disposed on the substrate.

10. The light-emitting diode chip of claim 9, further comprising at least one light emitting cell array in which the light-emitting cells are connected in series.

11. The light-emitting diode chip of claim 1, further comprising:

a reflective metal layer, the first and second DBRs being disposed between the reflective metal layer and the substrate; and

a protective layer, the reflective metal layer being disposed between the second DBR and the protective layer.

12. The light-emitting diode chip of claim 11, wherein:

the reflective metal layer comprises Al, Ag, or Rh; and

the protective layer comprises at least one of Ti, Cr, Ni, Pt, Ta, and Au.

13. The light-emitting diode chip of claim 1, wherein:

the first DBR comprises pairs of first material layers comprising a first optical thickness and second material layers comprising a second optical thickness;

the second DBR comprises pairs of third material layers comprising a third optical thickness and fourth material layers comprising a fourth optical thickness; and

the refractive index of the first material layers is different from the refractive index of the second material layers, and the refractive index of the third material layers is different from the refractive index of the fourth material layers.

14. The light-emitting diode chip of claim 13, wherein the first and second material layers comprise the same refractive index as the third and fourth material layers, respectively.

15. The light-emitting diode chip of claim 13, wherein the first optical thickness is thicker than the third optical thickness, and the second optical thickness is thicker than the fourth optical thickness.

16. The light-emitting diode chip of claim 13, wherein the first optical thickness and the second optical thickness are the same, and the third optical thickness and the fourth optical thickness are the same.

17. A method of fabricating a light-emitting diode chip configured to emit light of a first wavelength range and light of a second wavelength range, the method comprising:

forming a light-emitting structure on a first surface of a substrate, the light-emitting structure comprising;

an active layer disposed between a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, and configured to emit light of the first wavelength range;

controlling a surface roughness of a second surface of a substrate;

forming a phosphor layer configured to emit light of a red wavelength range on the light-emitting structure; and

forming first and second distributed Bragg reflectors (DBRs) on the second surface of the substrate,

wherein;

the first DBR is disposed closer to the substrate than the second DBR;

the first wavelength range comprises a blue wavelength range;

the first DBR comprises a higher reflectivity for light of the second wavelength range than for light of the first wavelength range; and

the second DBR comprises a higher reflectivity for light of the first wavelength range than for light of the second wavelength range.

18. The method of claim 17, wherein controlling the surface roughness of the second surface of the substrate comprises:

removing a portion of the substrate by grinding a second surface of the substrate; and

reducing the surface roughness of the second surface of the substrate by lapping the substrate.

19. The method of claim 18, wherein the controlling the surface roughness of the second surface of the substrate further comprises surface-processing the second surface of the substrate using a chemical after performing the lapping.

20. The method of claim 17, wherein forming the first and second DBRs on the second surface of the substrate comprises alternately disposing SiO₂ and TiO₂ on the surface roughness-controlled second surface of the substrate, and

wherein a layer of the first DBR closest to the substrate comprises TiO₂.