CALIBRATION OF A BST CAPACITOR CONTROL CIRCUIT

• US 20150207356A1
• Filed: 01/21/2015
• Published: 07/23/2015
• Est. Priority Date: 01/23/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: CHARLEY, Sylvain, MOINDRON, Laurent, HEURTIER, Jrme
• Granted Patent: US 9,293,939 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H01Q 5/335 at the feed, e.g. for impedance matching
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: H03J 3/04 Arrangements for compensating for variations of physical values, e.g. temperature

Abstract

A circuit for controlling a capacitor having a capacitance settable by biasing, including at least one terminal for receiving a digital set point value depending on the value desired for the capacitance, a circuit for determining a drift of the capacitance with respect to a nominal value, and a circuit of application of a correction to said digital set point value, depending on the determined drift.

Claims

1. A circuit configured to control a capacitor having a capacitance settable by a bias signal, comprising:

at least one terminal configured to receive a digital set point value depending on a value selected for the capacitance;

a determination circuit configured to determine a drift of the capacitance with respect to a nominal value; and

an adder circuit configured to apply a correction to said digital set point value, depending on the determined drift.

2. The circuit of claim 1, comprising:

a digital-to-analog converter configured to receive said corrected set point value; and

an amplifier configured to generate the bias signal for said capacitor.

3. The circuit of claim 2 wherein a switch connects an output terminal configured to deliver said bias signal, either to said determination circuit, or to the output of said amplifier.

4. The circuit of claim 1 wherein said determination circuit determines a duration for the capacitor to reach a charge threshold.

5. The circuit of claim 4 wherein said determination circuit causes a progressive charge of said capacitor.

6. The circuit of claim 1, comprising a terminal of connection of a reference capacitor.

7. The circuit of claim 1 wherein the correction is a percentage applied to the digital set point value.

8. A system, comprising:

a first capacitor having a settable capacitance, the capacitor having a first terminal; and

a control circuit coupled to the first terminal, the control circuit including;

a second terminal configured to receive a set point signal;

a calibration circuit configured to output a correction signal;

a combination circuit configured to receive the set point signal and the correction signal;

a signal processing chain coupled to combination circuit and the first terminal of the first capacitor to provide a bias signal to set the capacitor in a calibration phase.

9. The system of claim 8 wherein the signal processing chain includes a digital-to-analog converter coupled to the combination circuit and an amplifier coupled to the digital-to-analog converter and a first switch coupled between the amplifier and the first terminal of the first capacitor.

10. The system of claim 9 wherein the control circuit includes a second switch coupled between the first switch, the calibration circuit, and a third terminal.

11. The system of claim 10, further comprising a second capacitor that is coupled to the third terminal, the second capacitor being a reference capacitor.

12. The system of claim 8 wherein the calibration circuit includes:

a processing unit;

a current source coupled to the processing unit;

a third switch configured to be controlled by the current source;

an oscillator;

a counter coupled to the oscillator and the processing unit;

a delay circuit coupled to the oscillator;

a flip flop coupled to the delay circuit and the counter; and

a comparator having an output coupled to the flip flop, the comparator configured to receive a signal from the third switch and from the second switch at a first input, the comparator also configured to receive a reference voltage at a second input.

13. A device, comprising:

a control circuit having a calibration phase and an operating phase, the control circuit including;

a first terminal configured to output a bias signal to a capacitor in the calibration phase;

a second terminal configured to receive a set point signal;

a calibration circuit configured to output a correction signal;

a combination circuit configured to receive the set point signal and the correction signal;

a signal processing chain coupled to combination circuit and the first terminal to provide the bias signal in the calibration phase.

14. The device of claim 13 wherein the signal processing chain includes a digital-to-analog converter coupled to the combination circuit and an amplifier coupled to the digital-to-analog converter and a first switch coupled between the amplifier and the first terminal.

15. The device of claim 14 wherein the control circuit includes a second switch coupled between the first switch, the calibration circuit, and a third terminal.

16. The system of claim 13 wherein the calibration circuit includes:

a processing unit;

a current source coupled to the processing unit;

a third switch configured to be controlled by the current source;

an oscillator;

a counter coupled to the oscillator and the processing unit;

a delay circuit coupled to the oscillator;

a flip flop coupled to the delay circuit and the counter; and

a comparator having an output coupled to the flip flop, the comparator configured to receive a signal from the third switch and from the second switch at a first input, the comparator also configured to receive a reference voltage at a second input.