ELECTRONIC DEVICE OF VERTICAL MOS TYPE WITH TERMINATION TRENCHES HAVING VARIABLE DEPTH

• US 20150214300A1
• Filed: 01/29/2015
• Published: 07/30/2015
• Est. Priority Date: 01/29/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: BARLETTA, Giacomo, MAGR, Angelo
• Granted Patent: US 9,484,404 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area.

Claims

1. An electronic device, comprising:

a chip of semiconductor material having a main surface and a substrate region of said semiconductor material with a first type of conductivity extending from the main surface;

at least one vertical MOS transistor, formed in an active area of the chip, the transistor including;

at least one body region in the semiconductor material with a second conductivity type extending from the main surface in the substrate region;

one or more cells, each cell having;

a source region in the semiconductor material of the first conductivity type extending from the main surface in the body region;

a gate trench;

a gate region of electrically conductive material in the gate trench extending from the main surface in the body region and in the substrate region; and

an insulating gate layer electrically insulating the gate region from said semiconductor material; and

a termination structure including a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring including;

at least one termination trench extending from the main surface in the chip;

at least one floating element of electrically insulating material in the at least one termination trench; and

at least one bottom region of said semiconductor material of the second conductivity type extending from at least a deepest portion of a surface of the termination trench in the chip, wherein the termination trenches each have a depth from the main surface decreasing moving away from the active area.

2. The electronic device according to claim 1 wherein the termination structure includes an edge ring of said semiconductor material of the second conductivity type surrounding at least part of the active area on the main surface, the edge ring extending from the main surface in the substrate region to a depth lower than the depth of at least a deepest one of the termination trenches, and wherein the bottom region of said at least one deepest termination trench is separated from the edge ring.

3. The electronic device according to claim 1 wherein the termination structure includes an edge ring of said semiconductor material of the second conductivity type surrounding at least part of the active area on the main surface, the edge ring extending from the main surface in the substrate region to a depth lower than the depth of at least a deepest one of the termination trenches, and wherein the bottom region of each deepest termination trench reaches the edge ring and the bottom region of the termination trench of a first one of the termination rings being proximal to the active area reaches the body region.

4. The electronic device according to claim 1 wherein the depth of the termination trench of a first one of the termination rings being proximal to the active area is substantially equal to a depth of the gate trenches.

5. The electronic device according to claim 4 wherein the MOS transistor further includes a source contact of electrically conductive material in contact with the source regions and said semiconductor material between the termination trenches of at least one first pair of the termination rings being proximal to the active area.

6. The electronic device according to claim 1 wherein the MOS transistor further includes a field oxide layer on the main surface surrounding at least part of the active area, at least one least deep of the termination trenches being arranged in correspondence to the field oxide layer.

7. The electronic device according to claim 1 wherein a width of the termination trenches along a first direction from the active area decreases moving away from the active area,

8. The electronic device of claim 1 wherein a distance between each pair of adjacent termination structures increases moving away from the active area.

9. The electronic device of claim 1 wherein each termination structure includes a plurality of termination trenches including the at least one termination trench, a distance between each pair of termination trenches increasing moving away from the active area.

23. The device of claim 1 wherein the plurality of termination rings includes a first group of termination rings and a second group of termination rings, the first group being positioned between the at least one vertical MOS transistor and the second group of termination rings.

24. The device of claim 23, further comprising:

a protective layer on the main surface of the chip and on top surfaces of the first group of termination rings and the second group of termination rings;

a source metal layer on the protective layer, the source metal layer being in contact with the main surface between ones of the first group of termination rings.

25. The device of claim 24 wherein the source metal layer is configured to bias the substrate region of said semiconductor material that has the first type of conductivity.

26. The device of claim 25 wherein side and bottom surfaces of the second group of termination trenches are in the substrate region.

27. The device of claim 26 wherein bottom surfaces of the first group of termination trenches extend past the substrate region and portions of side surfaces of the first group of termination trenches are in the substrate region.

28. The device of claim 23, further comprising a protective layer on the main surface of the chip and on top surfaces of the first group of termination rings and the second group of termination rings and a source metal layer on the protective layer and isolated from the first group of termination rings and the second group of termination rings.

10. A method for manufacturing an electronic device integrated on a chip of semiconductor material having a main surface and a substrate region of said semiconductor material with a first type of conductivity extending from the main surface, the method comprising:

forming at least one vertical MOS transistor in an active area of the chip by;

forming at least one body region of said semiconductor material with a second conductivity type extending from the main surface in the substrate region;

forming one or more cells, for each cell;

forming a source region of said semiconductor material of the first conductivity type extending from the main surface in the body region;

forming a gate trench extending from the main surface in the body region and in the substrate region;

forming an insulating gate layer in the gate trench; and

forming a gate region of electrically conductive material in the gate trench being electrically insulated from said semiconductor material by the insulating gate layer; and

forming a termination structure including a plurality of termination rings surrounding at least part of the active area on the main surface, for each termination ring;

forming at least one termination trench extending from the main surface in the chip;

forming at least one floating element of electrically insulating material in the termination trench; and

forming at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip, wherein said forming a termination structure includes;

forming the termination trenches with a depth from the main surface decreasing moving away from the active area.

11. The method according to claim 10 wherein said forming the termination trenches includes:

forming a stack of masking layers superimposed one to another on the main surface, the masking layers being equal in number to the termination rings;

performing an etching operation for each termination ring by proceeding moving away from the active area, the etching operation selectively removing a portion of a free masking layer in correspondence to the termination trenches of the termination ring and of each previous termination ring; and

performing at least one further etching operation for each termination ring by proceeding moving away from the active area, the further etching operation selectively removing a portion of the semiconductor material in correspondence to the termination trenches of the termination ring and of each previous termination ring and selectively removing a portion of the free masking layer in correspondence to the termination trench of each next termination ring.

12. The method according to claim 11 wherein said forming a stack of masking layers includes:

forming a masking sub-layer and a further masking sub-layer superimposed to each other for each masking layer,

wherein said performing an etching operation for each termination ring includes, for each etching operation;

performing a first etching sub-operation, the first etching sub-operation being selective for the further masking sub-layer with respect to the masking sub-layer and having a length sufficient to remove each corresponding portion of the further masking sub-layer completely; and

performing a second etching sub-operation, the second etching sub-operation being selective for the masking sub-layer with respect to the further masking sub-layer and having a length sufficient to remove each corresponding portion of the masking sub-layer completely,

wherein said performing at least one further etching operation for each termination ring includes, for each one of said at least one further etching operation;

performing a further first etching sub-operation, the further first etching sub-operation being selective for the semiconductor material with respect to the further masking sub-layer and having a length corresponding to a depth of the termination trench of the corresponding termination ring for a last one of the termination rings and corresponding to a depth difference between the termination trench of the corresponding termination ring and the termination trench of a next one of the termination rings for each termination ring different from the last termination ring,

performing a further second etching sub-operation, the further second etching sub-operation being selective for the further masking sub-layer with respect to the semiconductor material and to the masking sub-layer and having a length sufficient to remove each corresponding portion of the further masking sub-layer completely; and

performing a further third etching sub-operation, the further third etching sub-operation being selective for the masking sub-layer with respect to the semiconductor material and to the further masking sub-layer and having a length sufficient to remove each corresponding portion of the masking sub-layer completely.

13. The method according to claim 10 wherein said forming the termination trenches includes:

performing an etching operation for each termination ring, the etching operation selectively removing said semiconductor material in correspondence to the termination trench of the termination ring and having a length corresponding to the depth of the termination trench of the termination ring.

14. The method according to claim 10 wherein a width of the termination trenches decreases moving away from the active area, said forming the termination trenches comprising:

performing an etching operation, the etching operation selectively removing said semiconductor material in correspondence to the termination trenches of all the termination rings and having a length corresponding to the depth of the terminating trenches as a function of the width thereof.

15. The method according to claim 10 wherein said forming a bottom region includes:

implanting impurities of the second conductivity type into the chip along an implantation direction perpendicular to the main surface.

16. The method according to claim 10 wherein said forming a bottom region includes implanting impurities along a plurality of implantation directions inclined with respect to the main surface.

17. A device, comprising:

a substrate having an outermost edge;

a transistor region in the substrate;

a termination structure formed in the substrate between the transistor region and the outermost edge, the termination structure including;

a plurality of insulating floating elements;

a plurality of termination trenches extending into the substrate, each trench including one of the plurality of insulating floating elements, each trench having a depth, the depth of each respective trench decreasing as the respective trench is further from the transistor region and closer to the outermost edge.

18. The device of claim 17 wherein each termination trench including a doped bottom region.

19. The device of claim 18 wherein each termination trench includes doped side regions that are coupled to the bottom regions.

20. The device of claim 17 wherein the termination trenches are each part of a termination rings that surrounds the transistor region.

21. The device of claim 17 wherein the substrate has a first conductivity type and each termination trench includes a doped bottom region of a second conductivity type.

22. The device of claim 21 wherein the transistor region includes a vertical MOS transistor, the transistor including:

a body region of the second conductivity type in the substrate;

a source region of the first conductivity type between a top surface of the substrate and the body region;

a gate trench;

a gate region in the gate trench extending; and

an insulating gate layer electrically insulating the gate region from the substrate.