SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

• US 20150221654A1
• Filed: 10/21/2014
• Published: 08/06/2015
• Est. Priority Date: 02/03/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Dong-Hyuk, SHIN, Geo-Myung, SHIN, Dong-Suk
• Granted Patent: US 9,847,224 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

Claims

1. A semiconductor device, comprising:

a substrate comprising a plurality of first active regions and a plurality of second active regions;

a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and

a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively,

wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

2. The semiconductor device of claim 1, wherein top surfaces of the first source/drain layers are formed at a substantially same height as top surfaces of the second source/drain layers.

3. The semiconductor device of claim 1, wherein a distance between the first active regions is smaller than a distance between the second active regions.

4. The semiconductor device of claim 1, further comprising a plurality of first and second spacers,

wherein the first spacers are formed along sidewalls of the first active regions, respectively, and the second spacers are formed along sidewalls of the second active regions, respectively, and

wherein top portions of the first spacers are formed to be higher than top portions of the second spacers.

5. The semiconductor device of claim 1, wherein the first gate structures and the first source/drain layers constitute at least one negative-channel metal oxide semiconductor (NMOS) transistor and one positive-channel metal oxide semiconductor (PMOS) transistor, and the second gate structures and the second source/drain layers constitute at least one NMOS transistor and one PMOS transistor.

6. A semiconductor device, comprising:

a substrate including a field region and first and second active regions, an isolation layer being formed on the field region, and the first and second active regions protruding from the isolation layer;

first and second gate structures on the first and second active regions, respectively;

first and second spacers on sidewalls of the first and second active regions, respectively, top surfaces of the first and second spacers being formed to be higher than those of the first and second active regions, respectively, and heights of the top surfaces of the first and second spacers being different from each other; and

first and second source/drain layers adjacent to the first and second gate structures on the first and second active regions, respectively, the first and second source/drain layers contacting the first and second spacers, respectively.

7. The semiconductor device of claim 6, wherein the first and second spacers are formed on both sidewalls of the first and second active regions, respectively, to define first and second recesses together with top surfaces of the first and second active regions, respectively, and

wherein the first and second source/drain layers fill the first and second recesses and protrude from the first and second spacers, respectively.

8. The semiconductor device of claim 7, wherein each of the first and second active regions extends in a second direction substantially parallel to a top surface of the substrate,

wherein a top surface of the first spacer is higher than that of the second spacer, and

wherein the first source/drain layer has a maximum width in a first direction smaller than that of the second source/drain layer, the first direction being substantially parallel to the top surface of the substrate and substantially perpendicular to the second direction.

9. The semiconductor device of claim 7, wherein top surfaces of the first and second source/drain layers are substantially coplanar with each other.

10. The semiconductor device of claim 6, wherein each of the first and second source/drain layers includes silicon-germanium doped with p-type impurities.

11. The semiconductor device of claim 6, wherein each of the first and second source/drain layers includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

12. The semiconductor device of claim 6, wherein the first active region includes a plurality of first active regions, each of which extends in a second direction substantially parallel to a top surface of the substrate, disposed at a first gap from each other in a first direction substantially parallel to the top surface of the substrate and substantially perpendicular to the second direction, and

wherein the second active region includes a plurality of second active regions, each of which extends in the second direction, disposed at a second gap from each other in the first direction, the second gap being greater than the first gap.

13. The semiconductor device of claim 12, wherein each of the first and second gate structures extends in the first and second direction, and

wherein the semiconductor device further comprises first and second gate spacers on both sidewalls of the first and second gate structures in the second direction, the first and second gate spacers including a material substantially the same as that of the first and second spacers.

14. The semiconductor device of claim 6, wherein each of the first and second gate structures includes a gate insulation layer pattern, a high-k dielectric layer pattern and a gate electrode sequentially stacked on the substrate.

15. The semiconductor device of claim 6, wherein the first active region is formed in a static random access memory (SRAM) region in which a SRAM device is formed, and the second active region is formed in a logic region in which a logic device is formed.

16. A method of manufacturing a semiconductor device, the method comprising:

forming an isolation layer on a substrate to define a field region and first and second active regions, the field region being covered by the isolation layer, and the first and second active regions not being covered by the isolation layer and protruding from the isolation layer;

forming first and second dummy gate structures on the first and second active regions, respectively;

forming first and second spacers on both sidewalls of the first and second active regions not covered by the first and second dummy gate structures, respectively, heights of top surfaces of the first and second spacers being different from each other;

removing upper portions of the first and second active regions not covered by the first and second dummy gate structures, respectively, to form first and second recesses defined by the first and second spacers, respectively; and

forming first and second source/drain layers which fills the first and second recesses and protrudes from the first and second spacers, respectively.

17. The method of claim 16, wherein the forming the first and second source/drain layers includes performing a selective epitaxial growth (SEG) process using the first and second active regions exposed by the first and second recesses as a seed.

18. The method of claim 17, wherein the first and second source/drain layers are formed to include silicon-germanium doped with p-type impurities.

19. The method of claim 16, wherein the forming the first and second spacers includes:

forming a spacer layer on the first and second dummy gate structures, the first and second active regions and the isolation layer;

forming a photoresist pattern covering the first active region and exposing the second active region;

partially etching a portion of the spacer layer on the second active region exposed by the photoresist pattern;

removing the photoresist pattern; and

anisotropically etching the spacer layer to form the first and second spacers, the first spacer having a first height on both sidewalls of the first active region, the second spacer having a second height on both sidewalls of the second active region, and the second height being lower than the first height.

20. The method of claim 16, wherein the anisotropically etching the spacer layer includes forming first and second gate spacers on sidewalls of the first and second dummy gate spacers, respectively, and

wherein the method further comprises:

forming an insulating interlayer covering the first and second source/drain layers and the first and second spacers, and surrounding the first and second dummy gate structures and the first and second gate spacers; and

replacing the first and second dummy gate structures by first and second gate structures, respectively.