ARRAY SUBSTRATE, MANUFACTURING METHOD OF ARRAY SUBSTRATE AND DISPLAY DEVICE

• US 20150221681A1
• Filed: 06/26/2013
• Published: 08/06/2015
• Est. Priority Date: 04/16/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Guo, Xiao, Jiang, Wei, Lv, Fengzhen, Chu, Songnan, Zhang, Xinxia, Xiang, Kang
• Granted Patent: US 9,653,492 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

Embodiments of the disclosure provide an array substrate, a manufacturing method of the array substrate and a display device. The array substrate includes a thin film transistor region and a display region. The thin film transistor region includes a thin film transistor and a black matrix, and the display region includes a common electrode.

Claims

1. An array substrate, comprising a thin film transistor region and a display region, wherein the thin film transistor region comprises a thin film transistor and a black matrix, and the display region comprises a common electrode.

2. The array substrate according to claim 1, wherein the thin film transistor region further comprises a first transparent conductive layer, the first transparent conductive layer in the thin film transistor region and the common electrode in the display region are provided in a same layer and are disconnected with each other, and the thin film transistor is provided above the first transparent conductive layer.

3. The array substrate according to claim 2, wherein the black matrix is provided between the first transparent conductive layer and the thin film transistor.

4. The array substrate according to claim 1, wherein the array substrate further comprises a first passivation insulating layer, the first passivation insulating layer is provided on the first transparent conductive layer in the thin film transistor region and is provided on the common electrode in the display region, and the first passivation insulating layer is provided below the black matrix in the thin film transistor region.

5. The array substrate according to claim 4, wherein the thin film transistor is of top gate type.

6. The array substrate according to claim 5, wherein

the array substrate further comprises a gate insulating layer, a second passivation insulating layer and a pixel electrode;

the gate insulating layer is provided below a gate electrode of the thin film transistor;

the second passivation insulating layer is provided on the gate electrode of the thin film transistor;

a via hole is provided in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

the pixel electrode is provided on the second passivation insulating layer and is connected with the drain electrode of the thin film transistor through the via hole.

12. A display device, comprising an array substrate according to claim 1.

13. The array substrate according to claim 2, wherein the array substrate further comprises a first passivation insulating layer, the first passivation insulating layer is provided on the first transparent conductive layer in the thin film transistor region and is provided on the common electrode in the display region, and the first passivation insulating layer is provided below the black matrix in the thin film transistor region.

14. The array substrate according to claim 13, wherein the thin film transistor is of top gate type.

15. The array substrate according to claim 14, wherein

the array substrate further comprises a gate insulating layer, a second passivation insulating layer and a pixel electrode;

the gate insulating layer is provided below a gate electrode of the thin film transistor;

the second passivation insulating layer is provided on the gate electrode of the thin film transistor;

a via hole is provided in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

the pixel electrode is provided on the second passivation insulating layer and is connected with the drain electrode of the thin film transistor through the via hole.

16. The array substrate according to claim 3, wherein the array substrate further comprises a first passivation insulating layer, the first passivation insulating layer is provided on the first transparent conductive layer in the thin film transistor region and is provided on the common electrode in the display region, and the first passivation insulating layer is provided below the black matrix in the thin film transistor region.

17. The array substrate according to claim 16, wherein the thin film transistor is of top gate type.

18. The array substrate according to claim 17, wherein

the array substrate further comprises a gate insulating layer, a second passivation insulating layer and a pixel electrode;

the gate insulating layer is provided below a gate electrode of the thin film transistor;

the second passivation insulating layer is provided on the gate electrode of the thin film transistor;

a via hole is provided in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

the pixel electrode is provided on the second passivation insulating layer and is connected with the drain electrode of the thin film transistor through the via hole.

7. A manufacturing method of an array substrate, wherein

the array substrate comprises a thin film transistor region and a display region, the thin film transistor region comprises a thin film transistor and a black matrix, and the display region comprises a common electrode;

and

the method comprises a step of;

forming a common electrode, a black matrix, and a semiconductor active layer, an ohmic contact layer, a drain electrode and a source electrode of the thin film transistor by a same patterning process.

8. The manufacturing method of the array substrate according to claim 7, wherein a first transparent conductive layer and a first passivation insulating layer are further formed during forming the common electrode, the black matrix, and the semiconductor active layer, the ohmic contact layer, the drain electrode and the source electrode of the thin film transistor by the same patterning process;

the first transparent conductive layer is provided in the thin film transistor region, and the first transparent conductive layer in the thin film transistor region and the common electrode in the display layer are provided in a same layer and are disconnected with each other; and

the first passivation insulating layer is provided on the first transparent conductive layer in the thin film transistor region and is provided on the common electrode in the display region, and the first passivation insulating layer is provided below the black matrix in the thin film transistor region.

9. The manufacturing method of the array substrate according to claim 8, wherein the step of forming the common electrode, the black matrix, and the semiconductor active layer, the ohmic contact layer, the drain electrode and the source electrode of the thin film transistor by the same patterning process comprises:

sequentially forming a first transparent conductive material layer, a first passivation insulating material layer, a black matrix layer, a semiconductor layer, a doped semiconductor layer, a source-drain metal layer on a base substrate, and applying a photoresist layer on the source-drain metal layer;

exposing and developing the photoresist layer to form photoresist regions with different thicknesses, wherein the photoresist in the display region have a first thickness, the photoresist in a connection region has a second thickness, the photoresist in an active region has a third thickness, and the photoresist in a source-drain region has a fourth thickness, the second thickness is larger than the first thickness, the third thickness is larger than the second thickness and the fourth thickness is larger than the third thickness, the connection region, the active region and the source-drain region are comprised in the thin film transistor region, the connection region is a region in the thin film transistor region other than the active region and the source-drain region, and the photoresist in the display region is disconnected with the photoresist in the connection region;

removing the source-drain metal layer in a region which is not covered by the photoresist;

removing the photoresist and exposed doped semiconductor layer by a thickness equal to that of the photoresist in the display region;

removing exposed source-drain metal layer;

removing the photoresist exposed doped semiconductor er and exposed semiconductor layer by a thickness equal to that of residual photoresist in the connection region;

removing exposed source-drain metal layer;

removing the photoresist, exposed doped semiconductor layer, exposed doped semiconductor layer, and exposed black matrix layer by a thickness equal to that of residual photoresist in the active region;

removing exposed source-drain metal layer in the active layer;

removing residual photoresist, exposed doped semiconductor layer, exposed semiconductor layer, exposed black matrix layer and exposed first passivation insulating material layer; and

removing exposed first transparent conductive material layer.

10. The manufacturing method of the array substrate according to claim 7, further comprising steps of:

forming a gate insulating layer and a gate electrode of the thin film transistor by a same patterning process;

forming a second passivation insulating layer by a same patterning process, and simultaneously forming a via hole in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

forming a pixel electrode by a same patterning process, wherein the pixel electrode is connected with the drain electrode of the thin film transistor through the via hole.

11. The manufacturing method of the array substrate according to claim 9, wherein the photoresist layer is exposed by a halftone mask or a gray-tone mask.

19. The manufacturing method of the array substrate according to claim 8, further comprising steps of:

forming a gate insulating layer and a gate electrode of the thin film transistor by a same patterning process;

forming a second passivation insulating layer by a same patterning process, and simultaneously forming a via hole in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

forming a pixel electrode by a same patterning process, wherein the pixel electrode is connected with the drain electrode of the thin film transistor through the via hole.

20. The manufacturing method of the array substrate according to claim 9, further comprising steps of:

forming a gate insulating layer and a gate electrode of the thin film transistor by a same patterning process;

forming a second passivation insulating layer by a same patterning process, and simultaneously forming a via hole in the gate insulating layer and the second passivation insulating layer above a drain electrode of the thin film transistor; and

forming a pixel electrode by a same patterning process, wherein the pixel electrode is connected with the drain electrode of the thin film transistor through the via hole.