FIELD EFFECT TRANSISTOR SWITCHING CIRCUIT

• US 20150222259A1
• Filed: 02/04/2014
• Published: 08/06/2015
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Nohra, George
• Granted Patent: US 9,379,698 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Embodiments include an apparatus, system, and method related to a switching circuit. In some embodiments, the switching circuit may include first switch including an n-channel field effect transistor (FET) in the signal path. The switching circuit may further include a second switch in shunt to the first switch. The second switch may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed.

Claims

1. A switching circuit comprising:

a first switch including an n-channel transistor; and

a second switch coupled with the first switch, the second switch including;

a first p-channel transistor including a first source contact, a first drain contact, a first gate contact, and a first body contact;

a second p-channel transistor coupled with the first p-channel transistor, the second p-channel transistor including a second source contact, a second drain contact, a second gate contact, and a second body contact, wherein the first gate contact is coupled with the second drain contact, and the first body contact is coupled with the second source contact; and

a first resistor and a second resistor both coupled with the second gate contact.

2. The switching circuit of claim 1, wherein the first resistor or the second resistor is a high-density resistor.

3. The switching circuit of claim 1, wherein the first p-channel transistor has a thickness of 1 millimeter (mm).

4. The switching circuit of claim 1, wherein the second p-channel transistor has a thickness of 3 micrometers (μ

m).

5. The switching circuit of claim 1, wherein the first source contact is coupled with a third switch that includes at least a third p-channel transistor and a fourth p-channel transistor.

6. The switching circuit of claim 1, wherein the first p-channel transistor or the second p-channel transistor is a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).

7. The switching circuit of claim 1, wherein the first gate contact is coupled with a direct current (DC) voltage input source.

8. The switching circuit of claim 1, wherein the first switch is coupled with the second switch such that the first p-channel transistor is directly coupled with the first switch and the first p-channel transistor is between the first switch and a ground contact of the switching circuit.

9. A method comprising:

coupling a gate contact of a first p-channel field effect transistor (FET) to a drain contact of a second p-channel FET;

coupling a body contact of the first p-channel FET to a source contact of the second p-channel FET;

coupling a gate contact of the second p-channel FET to a first resistor and a second resistor; and

coupling a drain contact of the first p-channel FET and the first resistor to an n-channel FET such that the first p-channel FET is electrically positioned between the n-channel FET and a ground.

10. The method of claim 9, wherein the first resistor or the second resistor is a high-density resistor.

11. The method of claim 9, wherein the first p-channel FET has a thickness of 1 millimeter (mm).

12. The method of claim 9, wherein the second p-channel FET has a thickness of 3 micrometers (μ

m).

13. The method of claim 9, wherein the first p-channel FET, the second p-channel FET, the first resistor, and the second resistor are a first switch, and a source contact of the first p-channel FET is coupled with a second switch that includes a third p-channel FET.

14. The method of claim 9, wherein the first p-channel FET or the second p-channel FET is a p-channel metal-oxide-semiconductor FET (MOSFET).

15. A system comprising:

a signal input;

a first switch electrically positioned between the signal input and a signal output, the first switch including an n-channel field effect transistor (FET); and

a second switch electrically coupled between the signal input and a ground, and electrically coupled between the first switch and the ground, wherein the second switch includes;

a first p-channel FET;

a second p-channel FET coupled with the first p-channel FET, the second p-channel FET including a drain contact coupled with a gate contact of the first p-channel FET, and a source contact coupled with a body contact of the first p-channel FET; and

a first resistor and a second resistor both coupled with a gate contact of the second p-channel FET.

16. The system of claim 15, wherein the first resistor or the second resistor are a high-density resistor.

17. The system of claim 15, wherein the first p-channel FET has a thickness of 1 millimeter (mm).

18. The system of claim 15, wherein the second p-channel FET has a thickness of 3 micrometers (μ

m).

19. The system of claim 15, further comprising a third switch include a third p-channel FET and a fourth p-channel FET, wherein a source contact of the first p-channel FET is coupled with a drain contact of the third p-channel FET.

20. The system of claim 15, wherein the first p-channel FET or the second p-channel FET are a p-channel metal-oxide-semiconductor FET (MOSFET).