Reduced Generation of Second Harmonics of FETs

• US 20150222260A1
• Filed: 02/06/2014
• Published: 08/06/2015
• Est. Priority Date: 02/06/2014
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Genc, Alper
• Granted Patent: US 9,461,037 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.

Claims

1. A field effect transistor device having reduced second-order harmonic distortion, including:

(a) a drain, a source, and a gate arranged on a body such that the gate modulates a conductive channel between a source region and a drain region; and

(b) added capacitance coupled to the body and at least one of the source or drain and sized to set the total capacitance from the source to the body to be essentially equal to the total capacitance from the drain to the body.

2. The field effect transistor device of claim 1, wherein the added capacitance has a value of less than about 1 pF.

3. A field effect transistor device having reduced second-order harmonic distortion, including:

(a) a drain, a source, and a gate arranged on a body such that the gate modulates a conductive channel between a source region and a drain region; and

(b) a voltage source coupled to the source and drain and configured at a voltage level sufficient to equalize the difference in the total capacitance from the source to the body with respect to the total capacitance from the drain to the body.

4. A field effect transistor device having reduced second-order harmonic distortion, including:

(a) a drain, a source, and a gate arranged on a body such that the gate modulates a conductive channel between a source region and a drain region; and

(b) equalizing means coupled and configured to equalize the total capacitance from the source to the body with respect to the total capacitance from the drain to the body.

5. A method for reducing second-order harmonic distortion in field effect transistor devices, including:

(a) providing a field effect transistor device having a drain, a source, and a gate arranged on a body such that the gate modulates a conductive channel between a source region and a drain region; and

(b) providing capacitance coupled to the body and at least one of the source and drain and sized to set the total capacitance from the source to the body to be essentially equal to the total capacitance from the drain to the body.

6. A method for reducing second-order harmonic distortion in field effect transistor devices, including:

(a) providing a field effect transistor device having a drain, a source, and a gate arranged on a body such that the gate modulates a conductive channel between a source region and a drain region; and

(b) providing a voltage source coupled to the source and drain and configured at a voltage level sufficient to equalize the total capacitance from the source to the body with respect to the total capacitance from the drain to the body.