ARRAY SUBSTRATE, PREPARATION METHOD FOR ARRAY SUBSTRATE, AND DISPLAY DEVICE

• US 20150236053A1
• Filed: 09/29/2014
• Published: 08/20/2015
• Est. Priority Date: 02/17/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: GUO, Jian, JIANG, Xiaohui, ZHANG, Jiaxiang, TIAN, Zongmin
• Granted Patent: US 9,583,508 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

The present invention discloses an array substrate, a preparation method for the array substrate, and a display device, wherein the array substrate comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, and a pixel electrode arranged on a substrate, the active layer includes an electric conduction area, a coverage area covered by the source electrode and the drain electrode, and an exposure area surrounding the coverage area, and the pixel electrode is lapped on the upper surfaces of the drain electrode, the exposure area of the active layer, and the gate insulation layer. According to the present invention, the pixel electrode breaks in the area, with the large gradient angle, of the drain electrode caused by slip-down due to gravity can be avoided, and the lap joint for the pixel electrode and the drain electrode is effectively facilitated.

Claims

1. An array substrate, comprising a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, and a pixel electrode which are arranged on a substrate, wherein the active layer includes an electric conduction area, a coverage area covered by the source electrode and the drain electrode, and an exposure area surrounding the outer side of the coverage area, and the pixel electrode is lapped on the upper surfaces of the drain electrode, the exposure area of the active layer, and the gate insulation layer.

2. The array substrate according to claim 1, wherein the width of the exposure area of the active layer is in a range of 0.5 μ

m-1.0 μ

m.

3. The array substrate according to claim 1, further comprising ohmic contact layers located between the active layer and the source electrode and the drain electrode, and the ohmic contact layers are covered by the source electrode and the drain electrode.

4. The array substrate according to claim 1, wherein the thickness of the coverage area of the active layer is greater than that of the exposure area of the active layer.

13. A display device, comprising an array substrate according to claim 1.

14. The display device according to claim 13, wherein the width of the exposure area of the active layer is in a range of 0.5 μ

m-1.0 μ

m.

15. The display device according to claim 13, wherein the array substrate further comprising ohmic contact layers located between the active layer and the source electrode and the drain electrode, and the ohmic contact layers are covered by the source electrode and the drain electrode.

16. The display device according to claim 13, wherein the thickness of the coverage area of the active layer is greater than that of the exposure area of the active layer.

5. A preparation method for the array substrate, comprising:

forming a pattern comprising a gate electrode, a gate insulation layer, and a pattern comprising an active layer on a substrate, and further comprising;

step 1;

forming a source electrode and a drain electrode by a patterning process, so that the active layer includes an electric conduction area, a coverage area covered by the source electrode and the drain electrode, and an exposure area surrounding the outer side of the coverage area; and

step 2;

forming a pixel electrode on the upper surfaces of the drain electrode, the exposure area of the active layer, and the gate insulation layer.

6. The preparation method for the array substrate according to claim 5, wherein the step 1 comprises:

step 101;

coating a layer of source-drain electrode layer film above the pattern of the active layer, coating photoresist on the source-drain electrode layer film, exposing and developing, and then etching the source-drain electrode layer film to form the source electrode and the drain electrode;

step 102;

treating the photoresist reserved on the source electrode and the drain electrode, so as to expose the source electrode and the drain electrode below the outer edge of the photoresist;

step 103;

etching the source electrode and the drain electrode exposed in step 102, so as to expose the active layer below the outer edges of the source electrode and the drain electrode to form the exposure area of the active layer; and

step 104;

stripping off the photoresist on the source electrode and the drain electrode.

7. The preparation method according to claim 6, wherein the step 102 comprises:

bombarding the photoresist by sulphur hexafluoride and oxygen to shrink the photoresist, so as to expose the source electrode and the drain electrode below the outer edge of the photoresist.

8. The preparation method according to claim 7, wherein the content of sulphur hexafluoride is in a range of 30-50 sccm, the content of oxygen is in a range of 1500-2500 sccm, a bombarding power is in a range of 4500-5500 W, and a treatment time is in a range of 30-40 s.

9. The preparation method for the array substrate according to claim 6, wherein the step 103 comprises:

etching the exposed source electrode and drain electrode by chlorine and oxygen.

10. The preparation method according to claim 9, wherein the content of chlorine is in a range of 800-1000 sccm, the content of oxygen is in a range of 1600-2000 sccm, a bombarding power is in a range of 3500-4500 W, a pressure is in a range of 30-40 mT, and a treatment time is in a range of 35-85 s.

11. The preparation method according to claim 6, wherein the step 101 further comprises:

forming a pattern comprising ohmic contact layers among the active layer, the source electrode and the drain electrode by the patterning process.

12. The preparation method for the array substrate according to claim 11, wherein the step 101 further comprises:

etching the ohmic contact layers by sulphur hexafluoride, chlorine and helium, so as to remove the ohmic contact layer corresponding to the electric conduction area of the active layer, and reserve the ohmic contact layer below areas corresponding to the source electrode and the drain electrode;

meanwhile, partially etching the exposure area of the active layer so that the thickness of the coverage area of the active layer is greater than that of the exposure area of the active layer.