DISPLAY DEVICE

• US 20150236054A1
• Filed: 04/30/2015
• Published: 08/20/2015
• Est. Priority Date: 09/19/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, AKIMOTO, Kengo, KOMORI, Shigeki, UOCHI, Hideki, FUTAMURA, Tomoya, KASAHARA, Takahiro
• Granted Patent: US 10,559,598 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Claims

1. (canceled)

2. A display device comprising:

a pixel portion comprising a pixel electrode;

a common wiring;

a protective circuit comprising a first thin film transistor and a second thin film transistor; and

a terminal portion configured to be connected to an FPC,

wherein the first thin film transistor includes;

a first gate electrode connected to the pixel portion;

a first gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the first gate electrode with the first gate insulating layer interposed therebetween;

a first conductive layer in contact with the first oxide semiconductor layer and connected to the pixel portion; and

a second conductive layer in contact with the first oxide semiconductor layer and connected to the common wiring,

wherein the second thin film transistor includes;

a second gate electrode connected to the common wiring;

a second gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the second gate electrode with the second gate insulating layer interposed therebetween;

a third conductive layer in contact with the second oxide semiconductor layer and connected to the pixel portion; and

a fourth conductive layer in contact with the second oxide semiconductor layer and connected to the common wiring, and

wherein the terminal portion includes;

a fifth conductive layer formed using a same conductive layer as the first to fourth conductive layers; and

a sixth conductive layer formed using a same conductive layer as the pixel electrode.

3. The display device according to claim 2,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer include indium, gallium, and zinc.

4. The display device according to claim 2,

wherein the first gate electrode, the first conductive layer, and the third conductive layer are connected to the pixel portion through a scan line.

5. The display device according to claim 2,

wherein the first gate electrode, the first conductive layer, and the third conductive layer are connected to the pixel portion through a signal line.

6. The display device according to claim 2,

wherein the first gate electrode, the first conductive layer, and the third conductive layer are connected to the pixel portion through a capacitor bus line.

7. A display device comprising:

a pixel portion comprising a pixel electrode;

a common wiring;

a protective circuit comprising a first thin film transistor, a second thin film transistor and a third thin film transistor; and

a terminal portion configured to be connected to an FPC,

wherein the first thin film transistor includes;

a first gate electrode;

a first gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the first gate electrode with the first gate insulating layer interposed therebetween;

a first conductive layer in contact with the first oxide semiconductor layer and connected to the pixel portion; and

a second conductive layer in contact with the first oxide semiconductor layer and connected to the common wiring,

wherein the second thin film transistor includes;

a second gate electrode connected to the pixel portion;

a second gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the second gate electrode with the second gate insulating layer interposed therebetween;

a third conductive layer in contact with the second oxide semiconductor layer and connected to the pixel portion; and

a fourth conductive layer in contact with the second oxide semiconductor layer and connected to the first gate electrode,

wherein the third thin film transistor includes;

a third gate electrode connected to the common wiring;

a third gate insulating layer over the third gate electrode;

a third oxide semiconductor layer over the third gate electrode with the third gate insulating layer interposed therebetween;

a fifth conductive layer in contact with the third oxide semiconductor layer and connected to the first gate electrode; and

a sixth conductive layer in contact with the third oxide semiconductor layer and connected to the common wiring,

wherein the terminal portion includes;

a seventh conductive layer formed using a same conductive layer as the first to sixth conductive layers; and

an eighth conductive layer formed using a same conductive layer as the pixel electrode.

8. The display device according to claim 7,

wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer include indium, gallium, and zinc.

9. The display device according to claim 7,

wherein the first conductive layer, the second gate electrode, and the third conductive layer are connected to the pixel portion through a scan line.

10. The display device according to claim 7,

wherein the first conductive layer, the second gate electrode, and the third conductive layer are connected to the pixel portion through a signal line.

11. The display device according to claim 7

wherein the first conductive layer, the second gate electrode, and the third conductive layer are connected to the pixel portion through a capacitor bus line.

12. A display device comprising:

a protective circuit;

a pixel; and

a terminal portion,

wherein the protective circuit includes a first transistor,

wherein the pixel includes a second transistor and a pixel electrode,

wherein the terminal portion includes a first conductive layer, a second conductive layer over the first conductive layer, and an FPC,

wherein the first transistor comprises;

a first gate electrode;

a gate insulating layer;

a first oxide semiconductor layer overlapping with the first gate electrode with the gate insulating layer interposed therebetween;

a first source electrode electrically connected to the first oxide semiconductor layer; and

a first drain electrode electrically connected to the first oxide semiconductor layer,

wherein the second transistor comprises;

a second gate electrode;

the gate insulating layer;

a second oxide semiconductor layer overlapping with the second gate electrode with the gate insulating layer interposed therebetween;

a second source electrode electrically connected to the second oxide semiconductor layer; and

a second drain electrode electrically connected to the second oxide semiconductor layer,

wherein the pixel electrode is electrically connected to one of the second source electrode and the second drain electrode,

wherein an insulating layer is positioned over the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the insulating layer includes oxygen,

wherein the first conductive layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed using a same conductive layer,

wherein the second conductive layer and the pixel electrode are formed using a same conductive layer, and

wherein the FPC is electrically connected to the first conductive layer through the second conductive layer.

13. The display device according to claim 12,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer include indium, gallium, and zinc.