SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20150236148A1
• Filed: 01/16/2015
• Published: 08/20/2015
• Est. Priority Date: 02/20/2014
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: MASUDA, Takeyoshi
• Granted Patent: US 9,647,106 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, a gate electrode, an interlayer insulating film, and a gate interconnection. The silicon carbide substrate includes: a first impurity region; a second impurity region provided on the first impurity region; and a third impurity region provided on the second impurity region so as to be separated from the first impurity region. A trench has a side portion and a bottom portion, the side portion extending to the first impurity region through the third impurity region and the second impurity region, the bottom portion being located in the first impurity region. When viewed in across section, the interlayer insulating film extends from above the third impurity region to above the gate electrode so as to cover the corner portion.

Claims

1. A silicon carbide semiconductor device comprising a silicon carbide substrate having a main surface,

said silicon carbide substrate including

a first impurity region that has a first conductivity type,

a second impurity region that is provided on said first impurity region and that has a second conductivity type different from said first conductivity type, and

a third impurity region that is provided on said second impurity region so as to be separated from said first impurity region, that forms said main surface, and that has said first conductivity type,

said main surface of said silicon carbide substrate being provided with a trench,

said trench having a side portion and a bottom portion, said side portion extending to said first impurity region through said third impurity region and said second impurity region, said bottom portion being located in said first impurity region,

the silicon carbide semiconductor device further comprising:

a gate insulating film in contact with a corner portion formed by said side portion and said main surface, said bottom portion, and said side portion;

a gate electrode in contact with said gate insulating film within said trench;

an interlayer insulating film in which an opening is formed to expose a portion of said gate electrode; and

a gate interconnection disposed in said opening and in contact with said gate electrode,

when viewed in a cross section, said interlayer insulating film extending from above said third impurity region to above said gate electrode so as to cover said corner portion.

2. The silicon carbide semiconductor device according to claim 1, wherein said gate interconnection is made of a material having a melting point of not less than 1000°

C.

3. The silicon carbide semiconductor device according to claim 2, wherein said material includes at least one material selected from a group consisting of W, Ni, WSi, and polysilicon.

4. The silicon carbide semiconductor device according to claim 1, wherein said interlayer insulating film has a carbon concentration smaller than a carbon concentration of said gate insulating film.

5. The silicon carbide semiconductor device according to claim 1, wherein said gate interconnection includes a barrier layer in contact with each of said gate electrode and said interlayer insulating film.

6. The silicon carbide semiconductor device according to claim 5, wherein said barrier layer includes at least one of Ti and TiN.

7. The silicon carbide semiconductor device according to claim 1, further comprising a gate pad in contact with said gate interconnection.

8. The silicon carbide semiconductor device according to claim 1, wherein said side portion of said trench includes a first plane having a plane orientation of {0-33-8}.

9. The silicon carbide semiconductor device according to claim 8, wherein said side portion of said trench microscopically includes said first plane, and said side portion microscopically further includes a second plane having a plane orientation of {0-11-1}.

10. The silicon carbide semiconductor device according to claim 9, wherein said first plane and said second plane of said side portion of said trench include a combined plane having a plane orientation of {0-11-2}.

11. The silicon carbide semiconductor device according to claim 10, wherein said side portion of said trench macroscopically has an off angle of 62°

±

10°

relative to a {000-1} plane.

12. A method for manufacturing a silicon carbide semiconductor device, comprising the step of preparing a silicon carbide substrate having a main surface,

said silicon carbide substrate including

a first impurity region that has a first conductivity type,

a second impurity region that is provided on said first impurity region and that has a second conductivity type different from said first conductivity type, and

a third impurity region that is provided on said second impurity region so as to be separated from said first impurity region, that forms said main surface, and that has said first conductivity type,

said main surface of said silicon carbide substrate being provided with a trench,

said trench having a side portion and a bottom. portion, said side portion extending to said first impurity region through said third impurity region and said second impurity region, said bottom portion being located, in said first impurity region,

the method for manufacturing the silicon carbide semiconductor device further comprising the steps of:

forming a gate insulating film in contact with a corner portion formed by said side portion and said main surface, said bottom portion, and said side portion;

forming a gate electrode in contact with said gate insulating film within said trench;

forming an interlayer insulating film in which an opening is formed to expose a portion of said gate electrode; and

forming a gate interconnection disposed in said opening and in contact with said gate electrode,

when viewed in a cross section, said interlayer insulating film extending from above said third impurity region to above said gate electrode so as to cover said corner portion.

13. The method for manufacturing the silicon carbide semiconductor device according to claim 12 wherein said gate insulating film is formed by thermally oxidizing said silicon carbide substrate in which said trench is formed.

14. The method for manufacturing the silicon carbide semiconductor device according to claim 12, wherein said interlayer insulating am is formed by a chemical vapor deposition method.

15. The method for manufacturing the silicon carbide semiconductor device according to claim 12, further comprising the step of forming an insulating layer in contact with said main surface of said silicon carbide substrate in which said trench is formed, wherein

in the step of forming said gate insulating film, said side portion and said bottom portion of said trench is thermally oxidized with said insulating layer being formed on said main surface.

16. The method for manufacturing the silicon carbide semiconductor device according to claim 12, wherein the step of forming said gate interconnection includes the step of forming a barrier layer in contact with each of said gate electrode and said interlayer insulating film.

17. The method for manufacturing the silicon carbide semiconductor device according to claim 16, wherein said barrier layer includes at least one of Ti and TiN.

18. The method for manufacturing the silicon carbide semiconductor device according to claim 12, further comprising the step of forming a gate pad in contact with said gate interconnection.

19. The method for manufacturing the silicon carbide semiconductor device according to claim 12, wherein said side portion of said trench includes a first plane having a plane orientation of {0-33-8}.

20. The method for manufacturing the silicon carbide semiconductor device according to claim 19, wherein said side portion of said trench microscopically includes said first plane, and said side portion microscopically further includes a second plane having a plane orientation of {0-11-1}.

21. The method for manufacturing the silicon carbide semiconductor device according to claim 20, wherein said first plane and said second plane of said side portion of said trench include a combined plane having a plane orientation of {0-11-2}.

22. The method for manufacturing the silicon carbide semiconductor device according to claim 21, wherein said side portion of said trench macroscopically has an off angle of 62°

±

10°

relative to a {000-1} plane.