SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150243501A1
• Filed: 08/29/2014
• Published: 08/27/2015
• Est. Priority Date: 02/27/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Thomason, Michael, Quddus, Mohammed Tanvir, Morgan, James, Mudholkar, Mihir, Donaldson, Scott, Grivna, Gordon M
• Granted Patent: US 9,552,993 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28537 Deposition of Schottky electrodes
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing may be deposited over the first layer. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

Claims

1. A method comprising:

depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises a first metal and a second metal;

depositing a second layer comprising a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing;

subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure; and

stripping at least a portion of the first structure to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

2. A method as set forth in claim 1 wherein the first metal comprises nickel and wherein the second metal comprises platinum.

3. A method as set forth in claim 2 wherein the nickel is 95 weight percent of the first layer and the platinum is 5 weight percent of the first layer.

4. A method as set forth in claim 2 wherein the nickel is 85 weight percent of the first layer and the platinum is 15 weight percent of the first layer.

5. A method as set forth in claim 2 wherein the nickel is 60 weight percent of the first layer and the platinum is 40 weight percent of the first layer.

6. A method as set forth in claim 1 wherein the first annealing act comprises exposing the first epi layer to a temperature ranging from 300°

C.-700°

C.

7. A method as set forth in claim 1 wherein the first annealing act is a rapid temperature annealing act exposing the first semiconductor epi layer to a temperature of approximately 300-700°

C. for approximately 45 seconds.

8. A method as set forth in claim 1 wherein the second layer comprising titanium.

9. A method as set forth in claim 8 wherein the first annealing act is a rapid temperature annealing act carried out in a nitrogen atmosphere furnace for approximately 45 seconds.

10. A method as set forth in claim 1 wherein the first annealing act is carried out in a furnace and exposes the first semiconductor epi layer to a temperature ranging from 300°

C.-450°

C.

11. A method as set forth in claim 10 wherein the first annealing act is carried out in a nitrogen atmosphere furnace for approximately 30 minutes.

12. A method as set forth in claim 1 wherein the stripping comprises exposing at least a portion of the first structure to a hot sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) mixture.

13. A method as set forth in claim 1 wherein the stripping comprises exposing at least a portion of the first structure to aqua regia.

14. A method comprising:

depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises nickel and platinum;

depositing a layer comprising a material constructed and arranged scavenge silicon migrating from the first semiconductor epi layer during annealing;

subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure; and

stripping at least a portion of the first structure to remove any silicide material formed by the first annealing act.

15. A method as set forth in claim 14 wherein the material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing comprises titanium.

16. A method comprising:

depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises a first metal and a second metal;

subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure; and

stripping at least a portion of the first structure to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

17. A method as set forth in claim 16 wherein the depositing a first layer on a semiconductor epi layer comprises placing the first semiconductor epi layer in a first deposition chamber and sputtering a first target having a first weight percent ratio of the first metal and second metal, and wherein the first annealing act exposes the first semiconductor epi layer to a first temperature range for a first time period range so that the first structure has a first barrier height, and further comprising:

depositing a second layer on a second semiconductor epi layer in an overlying position with respect to at least one trench device formed in the second semiconductor epi layer, wherein the depositing a second layer on a second semiconductor epi layer comprising placing the second semiconductor epi layer in the first deposition chamber and sputtering the first target having the first weight percent ratio of the first metal and second metal, and wherein the second layer comprises the first metal and the second metal;

subjecting the second semiconductor epi layer to at least a second annealing act to provide a second structure, and wherein the second annealing act exposes the second semiconductor epi layer to a second temperature range for a second time period range so that the second structure has a second barrier height different than the first barrier height;

stripping at least a portion of the second structure to remove to remove any of the second layer not reacted with silicon to form a silicide during the second annealing act.

18. A method as set forth in claim 16 wherein the first metal comprises nickel and wherein the second metal comprises platinum.

19. A method as set forth in claim 18 wherein the nickel is 95 weight percent of the first layer and the platinum is 5 weight percent of the first layer.

20. A method as set forth in claim 18 wherein the nickel is 85 weight percent of the first layer and the platinum is 15 weight percent of the first layer.