ADAPTIVE DEAD TIME CONTROL

• US 20150256074A1
• Filed: 09/02/2014
• Published: 09/10/2015
• Est. Priority Date: 03/04/2014
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Biondi, Tonio, Magazzu, Antonio
• Granted Patent: US 9,577,525 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0051 Diode reverse recovery losses
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 1/385 with means for correcting output voltage deviations introduced by the dead time
• CPC Class Codes: H02M 3/1566 with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A dead time detector detects when a dead time occurs in a switching regulator comprising a high-side switch and a low-side switch and generates an output signal based on a duration of the dead time. A first circuit generates a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse. A second circuit generates a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse. A controller generates drive signals to drive the high-side and low-side switches based on the first and second turn-on and turn-off signals.

Claims

1. A system comprising:

a dead time detector that detects when a dead time occurs and that generates an output signal based on a duration of the dead time, wherein the dead time is a period of time during which a high-side switch and a low-side switch of a switching regulator are turned off;

a first circuit that generates a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse;

a second circuit that generates a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse; and

a controller that generates a first gate drive signal to drive the high-side switch and a second gate drive signal to drive the low-side switch based on the first and second turn-on and turn-off signals.

2. The system of claim 1 wherein the duration of the dead time is a function of the first and second gate drive signals, and wherein the duration of the dead time is independent of a switching frequency of the switching regulator.

3. The system of claim 1 wherein the first and second circuits control the duration of the dead time by respectively advancing timings of the first and second turn-on signals or by delaying timings of the first and second turn-off signals.

4. The system of claim 1 wherein the dead time detector comprises a comparator that compares a threshold voltage to a voltage at a node where the high-side and low-side switches are connected in series and that generates the output signal including a current pulse based on the comparison.

5. The system of claim 1 wherein the dead time detector comprises:

a voltage amplifier that generates a differential voltage based on a threshold voltage and a voltage at a node where the high-side and low-side switches are connected in series; and

a transconductance amplifier that outputs a positive current as the output signal based on the differential voltage when the dead time occurs.

6. The system of claim 5 wherein a gain of the voltage amplifier is set according to a desired speed of the dead time detector.

7. The system of claim 5 wherein the transconductance amplifier outputs a negative current pulse as the output signal in absence of the dead time.

8. The system of claim 1 wherein the first circuit comprises:

a timer that generates a pulse having a predetermined pulse width in response to the first edge of the pulse width modulated pulse;

an integrator that performs a weighted time-integral of the output signal of the dead time detector over a time period equal to the predetermined pulse width and that generates an output voltage; and

a differential voltage-to-time converter that compares a reference voltage to the output voltage of the integrator and that generates the first turn-on and turn-off signals based on the comparison.

9. The system of claim 1 wherein the second circuit comprises:

a timer that generates a pulse having a predetermined pulse width in response to the second edge of the pulse width modulated pulse;

an integrator that performs a weighted time-integral of the output signal of the dead time detector over a time period equal to the predetermined pulse width and that generates an output voltage; and

a differential voltage-to-time converter that compares a reference voltage to the output voltage of the integrator and that generates the second turn-on and turn-off signals based on the comparison.

10. The system of claim 1 further comprising:

a first driver that drives the high-side switch based on the first gate drive signal and that generates a first feedback signal; and

a second driver that drives the low-side switch based on the second gate drive signal and that generates a second feedback signal,

wherein the controller receives the first and second feedback signals to prevent the high-side and low-side switches from turning on concurrently, and

wherein the controller controls the dead time by overriding the first and second feedback signals.

11. The system of claim 1 wherein the controller comprises a propagation delay control circuit that controls a propagation delay of the switching regulator by turning off the high-side and low-side switches when the pulse width modulated pulse changes state.

12. The system of claim 11, wherein the propagation delay is a delay between the first edge of the pulse width modulated pulse and a time when a voltage at a node where the high-side and low-side switches are connected in series changes in response to the first edge of the pulse width modulated pulse.

13. The system of claim 11, wherein the propagation delay is a delay between the second edge of the pulse width modulated pulse and a time when a voltage at a node where the high-side and low-side switches are connected in series changes in response to the second edge of the pulse width modulated pulse.

14. A method comprising:

detecting when a dead time occurs, wherein the dead time is a period of time during which a high-side switch and a low-side switch of a switching regulator are turned off;

generating an output signal based on a duration of the dead time;

generating a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse;

generating a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse; and

generating a first gate drive signal to drive the high-side switch and a second gate drive signal to drive the low-side switch based on the first and second turn-on and turn-off signals.

15. The method of claim 14 wherein the duration of the dead time is a function of the first and second gate drive signals, and wherein the duration of the dead time is independent of a switching frequency of the switching regulator.

16. The method of claim 14 further comprising controlling the duration of the dead time by respectively advancing timings of the first and second turn-on signals or by delaying timings of the first and second turn-off signals.

17. The method of claim 14 further comprising:

comparing a threshold voltage to a voltage at a node where the high-side and low-side switches are connected in series; and

generating the output signal including a current pulse based on the comparison.

18. The method of claim 14 further comprising:

generating a differential voltage based on a threshold voltage and a voltage at a node where the high-side and low-side switches are connected in series; and

outputting current as the output signal based on the differential voltage when the dead time occurs.

19. The method of claim 14 further comprising:

generating a pulse having a predetermined pulse width in response to the first edge of the pulse width modulated pulse;

integrating the output signal of the dead time detector over a time period equal to the predetermined pulse width and generating an output voltage;

comparing a reference voltage to the output voltage of the integrator; and

generating the first turn-on and turn-off signals based on the comparison.

20. The method of claim 14 further comprising:

generating a pulse having a predetermined pulse width in response to the second edge of the pulse width modulated pulse;

integrating the output current signal of the dead time detector over a time period equal to the predetermined pulse width and generating an output voltage;

comparing a reference voltage to the output voltage of the integrator; and

generating the second turn-on and turn-off signals based on the comparison.

21. The method of claim 14 further comprising:

driving the high-side switch based on the first gate drive signal;

driving the low-side switch based on the second gate drive signal;

generating first and second feedback signals to prevent the high-side and low-side switches from turning on concurrently; and

controlling the dead time by overriding the first and second feedback signals.

22. The method of claim 14 further comprising controlling a propagation delay of the switching regulator by turning off the high-side and low-side switches when the pulse width modulated pulse changes state.