INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS

• US 20150270393A1
• Filed: 03/19/2014
• Published: 09/24/2015
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kumar, Vinod
• Granted Patent: US 9,800,204 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Claims

1. An integrated circuit capacitor, comprising:

a silicon-on-insulator substrate including a buried oxide layer over a doped region;

a dual gate field effect transistor formed on the substrate, the dual gate field effect transistor having a primary gate and a secondary gate; and

a contact to the doped region, for use as the secondary gate of the dual gate field effect transistor.

2. The integrated circuit capacitor of claim 1 wherein the buried oxide layer has a thickness greater than the thickness of a primary gate oxide within the dual gate field effect transistor.

3. The integrated circuit capacitor of claim 1 wherein the buried oxide sustains application of 3.3 V to the doped region without experiencing a structural breakdown.

4. The integrated circuit capacitor of claim 1 wherein source and drain profiles of the dual gate field effect transistor are substantially vertical.

5. The integrated circuit capacitor of claim 1 wherein the secondary gate creates a channel between a source and a drain of the dual gate field effect transistor.

6. The integrated circuit capacitor of claim 1 wherein the secondary gate increases capacitance of the dual gate field effect transistor when operated at a lower bias voltage applied to the primary gate.

7. The integrated circuit capacitor of claim 1 wherein the secondary gate sustains a higher bias voltage than the primary gate.

8. The integrated circuit capacitor of claim 6 wherein capacitance formed by an oxide of the secondary gate is used as a de-coupling capacitor between two supply voltage nodes.

9. A method of making an integrated circuit capacitor, the method comprising:

providing a silicon-on-insulator substrate including a buried oxide layer over a doped region;

forming a field effect transistor on the substrate, the field effect transistor including source and drain regions that have substantially vertical profiles; and

forming a front side contact to the doped region.

10. A microcircuit, comprising:

a voltage supply;

an operational amplifier electrically coupled to the voltage supply, the operational amplifier having inverting and non-inverting input terminals and an output terminal; and

a capacitive PMOS field effect transistor coupled to the operational amplifier, the transistor including a doped substrate, and a buried oxide layer within the doped substrate.

11. The microcircuit of claim 10 wherein the capacitive PMOS field effect transistor is a dual gate device including primary and secondary gates.

12. The microcircuit of claim 10 wherein the primary and secondary gates of the PMOS field effect transistor are coupled to different voltages to create capacitance across the gates.

13. The microcircuit of claim 10, further comprising:

a transistor coupled between the output terminal and the current source;

a voltage divider coupled to the voltage supply and the non-inverting input terminal; and

a current source coupled to the inverting input terminal, the microcircuit being operable as a reference voltage generator.

14. A microcircuit, comprising:

a first stage that receives an input signal at an input frequency;

a second stage that produces an output signal at an output frequency, the output signal coupled to the first stage; and

a third stage including a pair of capacitors in the form of dual gate transistors, the third stage coupled between the first and second stages.

15. The microcircuit of claim 14 wherein the third stage is operable as a loop filter.

16. The microcircuit of claim 14 wherein the third stage further comprises a decoupling capacitor in the form of a dual gate transistor.

17. The microcircuit of claim 14 wherein

the first stage includes a phase frequency detector and a charge pump;

the second stage includes a PMOS FET and a current controlled oscillator; and

the microcircuit is operable as a charge pump phase locked loop circuit.

18. A method, comprising:

coupling a supply voltage to source and drain terminals of a dual gate PMOS transistor formed on a doped substrate that contains a buried oxide layer;

applying a bias voltage to a primary gate of the dual gate PMOS transistor to control current in a channel region between the source and drain terminals;

grounding the doped substrate via a secondary gate; and

operating the dual gate PMOS transistor as an integrated capacitor for use in analog microcircuits.

19. The method of claim 18 wherein the supply voltage is within the range of about 1.2-3.3 V.

20. A method, comprising:

grounding source and drain terminals of a dual gate NMOS transistor formed on a doped substrate that contains a buried oxide layer;

coupling a supply voltage to the doped substrate via a secondary gate;

applying a bias voltage to a primary gate of the dual gate NMOS transistor to control current in a channel region between the source and drain terminals; and

operating the dual gate NMOS transistor as an integrated capacitor for use in analog microcircuits.

21. The method of claim 20 wherein the supply voltage is within the range of about 1.2-3.3 V.