Bias Control for Stacked Transistor Configuration

  • US 20150270806A1
  • Filed: 02/19/2015
  • Published: 09/24/2015
  • Est. Priority Date: 12/28/2012
  • Status: Active Grant
First Claim
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1. A circuital arrangement comprising:

  • i) an amplifier comprising;

    stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

    an input port operatively connected to an input transistor of the stacked transistors;

    an output port operatively connected to the drain terminal of the output transistor; and

    a reference terminal operatively coupling the input transistor to a reference potential, wherein;

    the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

    ii) a gate bias circuit, 

    wherein;

    the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a desired voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the desired voltage at the source terminal of the each transistor being in correspondence of a desired distribution of a voltage at the drain terminal of the output transistor across the stacked transistors.

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