SEMICONDUCTOR DEVICE HAVING TEMPERATURE SENSOR CIRCUIT THAT DETECTS A TEMPERATURE RANGE UPPER LIMIT VALUE AND A TEMPERATURE RANGE LOWER LIMIT VALUE

• US 20150276500A1
• Filed: 04/30/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Granted Patent: US 9,772,232 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Claims

1. A device, comprising:

a temperature sensor circuit coupled to receive a count value, the temperature sensor circuit detects a temperature range upper limit value and a temperature range lower limit value.

2. The device of claim 1, wherein:

the temperature range lower limit value and the temperature range upper limit value is set in response to the count value provided by a counter circuit.

3. The device of claim 2, wherein:

the temperature sensor circuit provides a first count signal having a first logic level in response to the temperature of the device attaining the temperature range upper limit value; and

the counter circuit is coupled to receive the first count signal and incrementally change the count value in a first direction in response to the first count signal having the first logic level.

4. The device of claim 3, further including:

the temperature sensor circuit provides a second count signal having the first logic level in response to the temperature of the device attaining the temperature range lower limit value; and

the counter circuit is coupled to receive the second count signal and incrementally change the count value in a second direction in response to the second count signal having the first logic level.

5. The device of claim 3, wherein:

the temperature range upper limit value and the temperature range lower limit value changes in response to the incremental change in the count value.

6. The device of claim 5, further including:

the temperature sensor circuit includes a variable resistor coupled to receive the count value, the variable resistor includes a resistance value that changes in response to the incremental change of the count value.

7. The device of claim 6, wherein:

the temperature sensor circuit includes a first resistor coupled in series with the variable resistor; and

an insulated gate field effect transistor having a source terminal coupled to a first terminal of the first resistor and a drain terminal coupled to a second terminal of the first resistor and a gate terminal coupled to receive a select signal.

8. The device of claim 7, further including:

a selection circuit coupled to provide the select signal.

9. The device of claim 8, wherein:

the selection circuit is an oscillator circuit and the selection signal is an oscillating signal.

10. The device of claim 4, wherein:

the temperature sensor circuit includes

a temperature sensing portion coupled to receive the count value and provide a temperature detect signal;

a first signal output portion coupled to receive the temperature detect signal and provide the first count signal; and

a second signal output portion coupled to receive the temperature detect signal and provide the second count signal.

11. The device of claim 10, further including:

a selection circuit coupled to provide a selection signal wherein

the first signal output portion is disabled in response to the selection signal having a first selection signal logic level; and

the second signal output portion is disabled in response to the selection signal having a second selection signal logic level.

12. The device of claim 11, further including:

the selection circuit is an oscillator circuit and the selection signal is an oscillating signal.

13. The device of claim 10, further including:

a count limit detection circuit providing a first count limit signal having a first count limit logic level in response to the counter reaching a first count limit; and

the first temperature sensing output portion is coupled to receive the first count limit signal, the first temperature sensing output portion is disabled in response to the first count limit signal having the first count limit logic level.

14. The device of claim 13, wherein:

the count limit detection circuit providing a second count limit signal having a second count limit logic level in response to the counter reaching a second count limit; and

the second temperature sensing output portion is coupled to receive the the count limit signal, the second temperature sensing output portion is disabled in response to the second count limit signal having the second count limit logic level.

15. The device of claim 1, further including:

a count transition detector coupled to receive a least significant bit of the count value and provide a count transition signal as a pulse in response to a logic transition in the least significant bit of the count value.

16. The device of claim 15, further including:

a control circuit coupled to receive the count transition signal, the control circuit provides a read signal; and

a performance parameter table coupled to receive the read signal and the count value, the performance parameter table provides performance parameters addressed by the count value in response to the read signal.

17. The device of claim 16, further including:

latch circuits coupled to receive the performance parameters and a load signal and provide latched performance parameters wherein the control circuit provides the load signal.

18. The device of claim 17, further including:

performance parameter adjusted circuits coupled to receive the latched performance parameters, performance parameter adjusted circuits have operational aspects adjusted in response to the values of the latched performance parameters.

19. The device of claim 16, wherein:

the performance parameter table is a non-volatile memory.

20. The device of claim 1, wherein:

the device is a semiconductor device.