INTEGRATED CIRCUIT COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES

• US 20150287722A1
• Filed: 10/11/2013
• Published: 10/08/2015
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Giraud, Bastien, Flatresse, Philippe, Noel, Jean-Philippe, Pelloux-Prayer, Bertrand
• Granted Patent: US 9,911,737 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Claims

1-9. -9. (canceled)

10. An integrated circuit, comprising:

a semi-conductor substrate;

first and second cells, each comprising;

first and second field-effect transistors of FDSOI type, and, respectively, one being of pMOS type and the other being of nMOS type;

first and second semi-conducting ground planes, respectively placed under the first and second transistors;

a buried oxide layer extending between the first and second transistors on the one hand, and the first and second ground planes on the other hand;

first and second semi-conducting wells, placed respectively under the first and second ground planes and separating these ground planes from the semi-conducting substrate, the first well and the first ground plane exhibiting the same type of doping, the second well and the second ground plane exhibiting the same type of doping;

the first and second cells being adjoined to one another so that their first transistors are aligned in a first direction parallel to the substrate and their second transistors are aligned in the first direction;

the first and second wells of the first cell and the first well of the second cell exhibiting one and the same doping of a first type, and the second well of the second cell exhibiting a doping of a second type, opposite to the first type;

the integrated circuit furthermore comprising a control device for applying one and the same first electrical bias to the wells exhibiting the first type of doping and a second electrical bias distinct from the first bias to the well exhibiting the second type of doping;

the transistors of the first cell being configured to exhibit a first threshold voltage level, the transistors of the second cell being configured to exhibit a second threshold voltage level different from the first level.

11. The circuit as claimed in claim 10, in which the first transistor of the second cell exhibits a compensating technological parameter so that the threshold voltage of said transistor exhibits the same threshold voltage level as the second transistor of this second cell.

12. The circuit as claimed in claim 11, in which said technological parameter for compensating the threshold voltage of the first transistor of the second cell is chosen from among a group composed of the following characteristics:

the length of its channel is less than the channel length of the second transistor of the second cell;

its gate is formed of a material exhibiting a different work function from the material forming the gate of the second transistor of the second cell.

13. The circuit as claimed in claim 12, in which the length of the channel of the second transistor of the second cell is greater by 2 nm than the channel length of the first transistor of the second cell, in such a way that the first and the second transistors of the second cell exhibit one and the same threshold voltage level.

14. The circuit as claimed in claim 10, in which the control device is configured so that said same first electrical bias applied to the wells exhibiting the first type of doping is distinct from the electrical supply voltage (VDD) of the circuit and from the electrical ground (GND) of the circuit, so that the threshold voltage of the first transistor of the second cell exhibits one and the same threshold voltage level as the second transistor of this second cell.

15. The circuit as claimed in claim 10, in which the first and second types of dopings correspond, respectively, to dopings of n and p type.

16. The circuit as claimed in claim 15, in which the control device is configured to apply an electrical bias to the second well of the second cell different from the bias applied to the first well of the first cell.

17. The circuit as claimed in claim 16, in which the levels of the threshold voltages of the transistors of the second cell are less than the levels of the threshold voltages of the transistors of the first cell.

18. The circuit as claimed in claim 10, in which each of the first and second cells comprises a deep isolation trench extending in a direction perpendicular to the substrate, down to below the ground planes of these cells, the isolation trench separating the first transistors from the second transistors of said cells.

19. The circuit as claimed in claim 12, in which the length of the channel of the second transistor of the second cell is greater by 6 nm than the channel length of the first transistor of the second cell, in such a way that the first and the second transistors of the second cell exhibit one and the same threshold voltage level.