COGNITIVE ENERGY SAVING METHOD AND APPARATUS

• US 20150293579A1
• Filed: 05/29/2014
• Published: 10/15/2015
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Entropic Communications Incorporated (Maxlinear Incorporated)
• Inventors: Petrovic, Branislav, Jogadhenu, Sagar, Safdar, Abul Shams
• Granted Patent: US 10,162,403 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3231 Monitoring the presence, absence or movement of users
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Systems and methods for reducing the amount of power consumed by an electronic or electrical device by using collected knowledge of the operation of the device to determine when to place the device in an ultra-low power consumption mode.

Claims

1. A power control system comprising:

a) a power supply, the power supply providing power to a device; and

b) a processor module, the processor module having information regarding usage patterns of the device and determining from the usage patterns when the device is to enter an ultra-low power control (ULPC) mode.

2. The power control system of claim 1, further comprising a timing module, the timing module turning off the power supply when the power control system enters ULPC mode, the timing module comprising a low power control circuit, the low power circuit having a charge retaining device that maintains sufficient power when the power supply is turned off to power the functions of the low power control circuit.

3. The power control system of claim 2, wherein the timing module generates the information regarding usage patterns.

4. The power control system of claim 1, wherein the information regarding usage patterns is generated in a head-end external to the device.

5. The power control system of claim 1, wherein the information regarding usage patterns is generated in a gateway external to the device.

6. The power control system of claim 2, wherein the power supply is powered by an external power source and the timing module comprises a power switch for breaking the connection between the power supply and the external power source to turn the power supply off when the power control system enters ULPC mode.

7. The power control system of claim 1, wherein the power supply has an enable input which allows the power supply to be turned off during ULPC mode.

8. The power control system of claim 2, wherein the charge retaining device is a capacitor.

9. The power control system of claim 2, wherein the charge retaining device is a battery.

10. The power control system of claim 2, wherein the low power control circuit provides a control signal to turn the power supply on before the charge in the charge retaining device drops to a level that is no longer sufficient to power the functions of the low power control circuit, the power supply restoring a charge to the charge retaining device when power is turned back on.

11. The power control system of claim 6, further comprising a second power supply, and wherein the timing module comprises a low power control circuit, the low power control circuit being powered by the second power supply.

12. The power control system of claim 10, wherein the functions of the low power control circuit include determining when to turn the power supply back on.

13. The power control system of claim 12, the low power control circuit further including a timer, and wherein determining when to turn the power supply back on is made based the timer.

14. The power control system of claim 12, further including a user activated switch coupled to the low power control circuit, activation of the user activated switch causing the low power control circuit to turn the power supply back on.

15. The power control system of claim 12, the functions of the low power control circuit include monitoring the state of at least one environmental sensor, the state of the environmental sensor being used to determine when to turn the power supply back on.

16. The power control system of claim 2, the processor module further determining when to enter and exit ULPC mode based upon the chances of achieving particular predetermined power consumption goals, the information regarding usage patterns being used to more aggressively select times at which it is likely that the user will not be actively using the device and place the power control system in ULPC mode during such selected times to make achieving the particular goals more likely.

17. The power control system of claim 3, wherein the timing module records failed attempts to turn the power supply on.

18. The power control system of claim 17, wherein the timing module detects when an external power source has been reconnected to the device and turns the power supply on upon detecting that an external power source has been reconnected to the device.

19. A device comprising:

a) a power supply; and

b) an integrated circuit comprising;

i) a power grid;

ii) an integrated circuit (IC) processor, the IC processor having information regarding usage patterns of the device and determining from the usage patterns when the integrated circuit is to enter an ultra-low power control (ULPC) mode;

iii) a first always-on power island isolated from the power grid, the always-on power island including a standby processor; and

iv) a first timing module, the first timing module residing on a second always-on power island isolated from the first always-on power island and the power grid, the first timing module having a switch that disconnects the power grid from the power supply when the integrated circuit enters ULPC mode and reconnects the power grid to the power supply when17 the integrated circuit exits ULPC mode, the first timing module coupled to the IC processor, the timing module receiving signals from the IC processor to enter ULPC mode, timing module having a timer set by the IC processor to determine the amount of time the integrated circuit will remain in ULPC mode, and timing module coupled to the standby processor and receiving a signal from the standby processor to exit ULPC mode prior to the timer timing out, the timing module further having a charge retaining device from which the timing module and the first always-on power island are powered during ULPC mode.

20. The device of claim 19, further including a second timing module, the second timing module comprising:

a) a switch coupled to the power supply for turning the power supply on and off; and

b) a low power control circuit, the low power control circuit having a timer and a charge retaining device, the low power control circuit coupled to the IC processor and receiving from the IC processor a ULPC control signal, the low power control circuit coupled to the switch and providing a switch control signal to the switch to cause the switch to turn the power supply off in response to the ULPC control signal, and providing the switch control signal to the switch to turn the power supply on in response to the timer;

wherein the IC processor determines when to send the ULPC control signal to the low power control circuit based on the information regarding usage patterns.

21. The device of claim 19, the always-on power island further including a plurality of interface modules, each interface module monitoring one or more of the environmental sensors, the interface module sending a signal to the standby processor when the state of one of the environmental sensors change, and the standby module sending a signal to the timing module to exit ULPC mode when the state of one of the environmental sensors changes.

22. A method of controlling power consumption in a device, the method comprising:

a) receiving information regarding usage patterns for the device; and

b) using the usage patterns to determine whether to enter into an ultra low power consumption (ULPC) mode.

23. The method of claim 22, wherein the device is powered by a power supply coupled to an external power source and entering into ULPC mode includes disconnecting the power supply from the external power source, and the method further comprising maintaining power to a low power control circuit, the power being provided by a charge retaining device that is isolated from the power supply.

24. A non-transitory, tangible computer readable medium having instruction stored there on, when executed, the instruction causing a processor to:

a) receive information regarding usage patterns for the device; and

b) using the usage patterns to determine whether to enter into an ultra low power consumption (ULPC) mode.

25. The non-transitory, tangible computer readable medium of claim 24, wherein the processor is powered by a power supply coupled to an external power source and entering into ULPC mode includes disconnecting the power supply from the external power source, and wherein power is maintained to a low power control circuit, the power being provided by a charge retaining device that is isolated from the power supply.