Ultrasonic Transducers in Complementary Metal Oxide Semiconductor (CMOS) Wafers and Related Apparatus and Methods

• US 20150298170A1
• Filed: 04/17/2015
• Published: 10/22/2015
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Sanchez, Nevada J., Alie, Susan A.
• Granted Patent: US 9,505,030 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61B 8/00 Diagnosis using ultrasonic, sonic or infrasonic waves imaging of objects using sonar G01S15/00
• CPC Class Codes: A61B 8/4494 characterised by the arrangement of the transducer elements devices for short-range imaging using particular transducer elements arrangements under G01S15/8909; arrangements of transducers in generation of mechanical vibrations of infrasonic, sonic or ultrasonic frequency B06B1/0607
• CPC Class Codes: B06B 1/02 making use of electrical energy B06B1/18, B06B1/20 take precedence
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 2201/51 Electrostatic transducer
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0617 : comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors

Abstract

Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Claims

1. A complementary metal oxide semiconductor (CMOS) wafer, comprising:

a semiconductor substrate;

an ultrasonic transducer comprising

a cavity representing a removed first metallization layer of the CMOS wafer;

an electrode disposed between the cavity and the semiconductor substrate; and

an acoustic membrane of the CMOS wafer comprising a dielectric layer and a second metallization layer of the CMOS wafer, the cavity being disposed between the semiconductor substrate and the acoustic membrane; and

integrated circuitry on the semiconductor substrate, coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer.

2. The CMOS wafer of claim 1, wherein the electrode disposed between the cavity and the semiconductor substrate is a first electrode of the ultrasonic transducer, and wherein the ultrasonic transducer further comprises a second electrode disposed opposite the first electrode.

3. The CMOS wafer of claim 1, wherein the electrode disposed between the cavity and the semiconductor substrate represents a liner layer of the removed first metallization layer of the CMOS wafer.

4. The CMOS wafer of claim 1, wherein the electrode disposed between the cavity and the semiconductor substrate is a bottom electrode of the ultrasonic transducer, and wherein the ultrasonic transducer further comprises a top electrode, with the cavity being disposed between the bottom electrode and the top electrode, and wherein the bottom and top electrodes represent liner layers of the removed first metallization layer of the CMOS wafer.

5. The CMOS wafer of claim 1, wherein the acoustic membrane of the CMOS wafer comprises one or more conductive vias.

6. The CMOS wafer of claim 5, wherein the electrode disposed between the cavity and the semiconductor substrate is a first electrode of the ultrasonic transducer, and wherein the ultrasonic transducer further comprises a second electrode disposed opposite the first electrode.

7. The CMOS wafer of claim 6, wherein at least one of the one or more conductive vias of the acoustic membrane is electrically connected to the second electrode.

8. The CMOS wafer of claim 1, further comprising at least one filled access hole passing through at least part of the acoustic membrane to the cavity.

9. The CMOS wafer of claim 1, comprising a plurality of ultrasonic transducers including the ultrasonic transducer.

10. The CMOS wafer of claim 1, wherein the second metallization layer is embedded within the dielectric layer of the acoustic membrane.

11. The CMOS wafer of claim 1, further comprising at least one hole positioned to not pass through the acoustic membrane.

12. A complementary metal oxide semiconductor (CMOS) wafer, comprising:

a semiconductor substrate;

a first metallization layer; and

an ultrasonic transducer comprising;

a cavity formed in the first metallization layer;

an electrode disposed between the cavity and the semiconductor substrate; and

an acoustic membrane of the CMOS wafer comprising a dielectric layer and a second metallization layer of the CMOS wafer, the cavity being disposed between the semiconductor substrate and the acoustic membrane; and

integrated circuitry on the semiconductor substrate, coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer.

13. The complementary metal oxide semiconductor (CMOS) wafer of claim 12, wherein the first metallization layer is configured to transmit electrical signals in a peripheral area of the substrate.

14. The complementary metal oxide semiconductor (CMOS) wafer of claim 12, wherein the first metallization layer has a plurality of cavities formed therein, and wherein each cavity corresponds to a different ultrasonic transducer.

15. A method, comprising:

forming an acoustic membrane of an ultrasonic transducer in a complementary metal oxide semiconductor (CMOS) wafer by stacking multiple layers of the CMOS wafer including at least one dielectric layer and a first metallization layer of the CMOS wafer;

forming at least one access hole to a second metallization layer of the CMOS wafer, the second metallization layer comprising an inner metal layer bounded by first and second conductive liner layers;

forming a cavity in the CMOS wafer by removing at least a portion of the inner metal layer of the first metallization layer through the at least one access hole using a selective etch, thereby releasing the acoustic membrane while substantially retaining the first and second conductive liner layers;

sealing the at least one access hole with an insulating material; and

coupling the first and second conductive liner layers to integrated circuitry of the CMOS wafer.

16. The method of claim 15, wherein forming the acoustic membrane further comprises coupling the first metallization layer of the CMOS wafer to the first conductive liner layer of the second metallization layer with one or more conductive vias.

17. The method of claim 15, wherein coupling the first and second conductive liner layers to integrated circuitry of the CMOS wafer comprises coupling the first conductive liner layer to integrated circuitry in a semiconductor substrate of the CMOS wafer by one or more conductive vias.

18. The method of claim 15, wherein the inner metal layer comprises aluminum, and wherein using a selective etch comprises using a hydrofluoric acid etch.

19. The method of claim 18, wherein the first and second conductive liner layers comprise titanium nitride (TiN).